PDF AD1981B Data sheet ( Hoja de datos )

Número de pieza	AD1981B
Descripción	AC 97 SoundMAX Codec
Fabricantes	Analog Devices
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No Preview Available ! a AC ’97 SoundMAX® Codec AD1981B FEATURES AC ’97 2.3 COMPATIBLE FEATURES S/PDIF Output, 20 Bits Data Format, Supporting 48 kHz and 44.1 kHz Sample Rates Integrated Stereo Headphone Amplifier Variable Sample Rate Audio External Audio Power-Down Control Greater than 90 dB Dynamic Range Stereo Full-Duplex Codec 20-Bit PCM DAC 3 Analog Line-Level Stereo Inputs for Line-In, AUX, and CD Mono Line-Level Phone Input Dual MIC Input with Built-In Programmable Preamp High Quality CD Input with Ground Sense Mono Output for Speakerphone or Internal Speaker Power Management Support 48-Lead LQFP Package, Lead-Free Available ENHANCED FEATURES Stereo MIC Preamps Support Built-In Digital Equalizer Function for Optimized Speaker Sound Full-Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software Programmed VREFOUT Output for Biasing Microphone and External Power Amp Split Power Supplies: 3.3 V Digital and 5 V Analog Multiple Codec Configuration Options MIC1 MIC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R MONO_OUT HP_OUT_L LINE_OUT_L LINE_OUT_R HP_OUT_R AD1981B MIC PREAMP G G CD DIFF AMP FUNCTIONAL BLOCK DIAGRAM VREFOUT VREF G VOLTAGE REFERENCE CODEC CORE GM GM PCM L/R ADC RATE 16-BIT ⌺-⌬ ADC 16-BIT ⌺-⌬ ADC XTL_OUT XTL_IN SPDIF SPDIF TX PLL ID0 ID1 MA HP M A MZ A MZ A HP M A GM GM 16-BIT ⌺-⌬ ADC 16-BIT ⌺-⌬ ADC M GA 20-BIT ⌺-⌬ DAC GA GA GA GA MM MM M GA GA GA GA MM MM M GA G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z 20-BIT ⌺-⌬ DAC PCM FRONT DAC RATE M ADC AND DAC SLOT LOGIC EQ EQ RESET SYNC BIT_CLK SDATA_OUT SDATA_IN AC '97 CONTROL REGISTERS ANALOG MIXING CONTROL LOGIC EAPD REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. JS0 JS1 EAPD One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. 1 page AD1981B tRST_LOW tRST2CLK RESET BIT_CLK SDATA_IN tTRI2ACTV tTRI2ACTV Figure 1. Cold Reset Timing (Codec Is Supplying the BIT_CLK Signal) tSYNC_HIGH tSYNC2CLK SYNC BIT_CLK Figure 2. Warm Reset Timing BIT_CLK tCLK_LOW tCLK_HIGH tCLK_PERIOD tSYNC_LOW SYNC tSYNC_HIGH tSYNC_PERIOD Figure 3. Clock Timing BIT_CLK tRISECLK tFALLCLK SYNC tRISESYNC tFALLSYNC SDATA_IN tRISEDIN tFALLDIN SDATA_OUT tRISEDOUT tFALLDOUT Figure 4. Signal Rise and Fall Times REV. B –5– 5 Page AD1981B Headphones Volume Register (Index 04h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 04h Headphone HPM X X LHV LHV LHV LHV LHV RM* X X RHV RHV RHV RHV RHV 8000h Volume 43 2 1 0 432 1 0 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table I for examples. This register controls the headphone volume controls for both stereo channels and mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automati- cally set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1. RHV [4:0] RM LHV [4:0] HPM Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the HPM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Headphones Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel. Table I. Volume Settings for Master and Headphone Reg. 76h Control Bits Master Volume (02h) and Headphone Volume (04h) MSPLT Left Channel Volume D[13:8] Right Channel Volume D[5:0] D15 WRITE READBACK Function D7* WRITE READBACK Function 0 0 00 0000 00 0000 0 dB Gain x 00 0000 00 0000 0 dB Gain 0 0 00 1111 00 1111 –22.5 dB Gain x 00 1111 00 1111 –22.5 dB Gain 0 0 01 1111 01 1111 –46.5 dB Gain x 01 1111 01 1111 –46.5 dB Gain 0 0 1x xxxx 01 1111 –46.5 dB Gain x 1x xxxx 01 1111 –46.5 dB Gain 0 1 xx xxxx xx xxxx –ϱ dB Gain, Muted x xx xxxx xx xxxx –ϱ dB Gain, Muted 1 0 1x xxxx 01 1111 –46.5 dB Gain 1 xx xxxx xx xxxx –ϱ dB Gain, Right Only Muted 1 1 xx xxxx xx xxxx –ϱ dB Gain, Left Only Muted 0 xx xxxx xx xxxx –46.5 dB Gain 1 1 xx xxxx xx xxxx –ϱ dB Gain, Left Muted 1 xx xxxx xx xxxx –ϱ dB Gain, Right Muted *For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. X in the above table is a wild card and has no effect on the value. REV. B –11– 11 Page

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