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PDF AD1959 Data sheet ( Hoja de datos )
| Número de pieza | AD1959 | |
| Descripción | PLL/Multibit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD1959 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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FEATURES
5 V Stereo Audio DAC System
Accepts 16-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Sigma-Delta Modulator with Data Directed
Scrambling
Single-Ended Output for Easy Application
–94 dB THD + N
108 dB SNR and Dynamic Range
75 dB Stopband Attenuation
Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis and
Output Phase
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
and 48 kHz Sample Rates
Programmable Dual Fractional-N PLL Clock Generator
27 MHz Master Clock Input/Oscillator
Generated System Clocks
SCLK0: 33.8688 MHz
SCLK1: 384/256 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/
96 kHz)
SCLK2: 512 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/
96 kHz)/22.5792 MHz
Better than 100 ps RMS Clock Jitter
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible, and DSP Serial Port Modes
28-Lead SSOP Plastic Package
PLL/Multibit ⌺-⌬ DAC
AD1959
APPLICATIONS
DVD, CD, Home Theater Systems, Automotive Audio
Systems, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1959 is a complete high-performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, digital interpolation filters, and analog output
drive circuitry with an on-board dual PLL clock generator.
Other features include an on-chip stereo attenuator and mute,
programmed through an SPI-compatible serial control port.
The AD1959 is fully compatible with all known DVD formats
including 96 kHz and 192 kHz sample frequencies and 24 bits.
It also is backwards-compatible by supporting 50 µs/15 µs
digital de-emphasis for “redbook” compact discs, as well as
de-emphasis at 32 kHz and 48 kHz sample rates.
The AD1959 has a simple but flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1959 can be configured in left-justified, I2S, right-justified,
or DSP serial-port-compatible modes. It can support 16, 20,
and 24 bits in all modes. The AD1959 accepts serial audio data
in MSB first, two’s-complement format, and operates from a
single 5 V power supply. It is fabricated on a single monolithic
integrated circuit and housed in a 28-lead SSOP package for
operation over the temperature range –40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
XIN XOUT MCLK
LOOP CLOCK
FILTERS OUTPUTS
23
CONTROL DATA
INPUT
3
AD1959
OSC
PLL
CIRCUIT
SERIAL CONTROL
INTERFACE
VOLTAGE
REFERENCE
16-/20-/24-
BIT DIGITAL
DATA INPUT
3
SERIAL
DATA
INTERFACE
ATTEN/MUTE
ATTEN/MUTE
8 ؋ FS
INTERPOLATOR
8 ؋ FS
INTERPOLATOR
MULTIBIT
SIGMA-DELTA
MODULATOR
MULTIBIT
SIGMA-DELTA
MODULATOR
DAC
DAC
OUTPUT
BUFFER
OUTPUT
BUFFER
L
ANALOG
OUTPUTS
R
REV. 0
RESET MUTE ZERO FLAG
2
PLL SUPPLY
2
DIGITAL SUPPLY
3
ANALOG SUPPLY
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
AD1959
PIN FUNCTION DESCRIPTIONS
Pin Input/Output Mnemonic
1I
CCLK
2I
3I
CLATCH
RESET
4I
5I
6I
7I
8I
9O
10 I/O
11 O
12 I
13 O
14 O
15
16
17
18
19
20 O
21 O
22 I
23 O
24
25
26 O
27 I
28 I
LRCLK
BCLK
SDATA
DVDD
DGND
SCLK0
MCLK
XOUT
XIN
SCLK1
SCLK2
PVDD
PGND
LF0
LF1
AGND0
OUTR
FILTR
AGND1
OUTL
AVDD
FILTB
ZERO
MUTE
CDATA
Description
Control Clock Input for Control Data. Control input data must be valid on
the rising edge of CCLK. CCLK may be continuous or gated.
Latch Input for Control Data.
Reset. The AD1959 is placed in a reset mode when this pin is held LO.
The serial control port registers are reset to their default values. Set HI for
normal operation.
Left/Right Clock Input for Input Data. Must run continuously.
Bit Clock Input for Input Data. Need not run continuously; may be gated
or used in a burst fashion.
Serial input, MSB first, containing two channels of 16/20/24 bits of two’s-
complement data per channel.
Digital Power Supply Connect to Digital 5 V Supply.
Digital Ground.
33.8688 MHz Clock Output.
27 MHz Master Clock Output/256 fS DAC Clock Input.
27 MHz Crystal Oscillator Output.
27 MHz Crystal Oscillator/External Clock Input.
256/384 fS Output.
512 fS/22.5792 MHz Output.
PLL Power Supply. Connect to PLL 5 V Supply.
PLL Ground.
PLL0 Loop Filter.
PLL1 Loop Filter.
Analog Ground.
Right Channel Positive Line Level Analog Output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND.
Analog Ground.
Left Channel Line Level Analog Output.
Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection, Connect 10 µF Capacitor to AGND.
Zero Flag Output. This pin goes HI when both channels have zero signal
input for more than 1024 L/R Clock Cycles.
Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for
normal operation.
Serial control input, MSB first, containing 16 bits of unsigned data
per channel.
REV. 0
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD1959.PDF ] | |
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