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PDF AD1958 Data sheet ( Hoja de datos )
| Número de pieza | AD1958 | |
| Descripción | PLL/Multibit DAC | |
| Fabricantes | Analog Devices | |
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a
PLL/Multibit ⌺-⌬ DAC
AD1958
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Single-Ended Output for Easy Use
108 dB Signal-to-Noise (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
109 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
–96 dB THD + N (Stereo)
75 dB Stop Band Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
and 48 kHz Sample Rates
Programmable Dual Fractional-N PLL Clock Generator
27 MHz Master Clock Oscillator
Better than 100 ps rms Master Clock Jitter
Generated System Clocks
SCLK0: 33.8688 MHz
SCLK1: 22.5792 MHz, 24.576 MHz, 33.8688 MHz, or
36.864 MHz
SCLK2: 16.9344 MHz
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible, and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Home Theater Systems, Automotive Audio
Systems, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1958 is a complete high-performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, digital interpolation filters, and analog output
drive circuitry with an on-board dual PLL clock generator.
Other features include an on-chip stereo attenuator and mute,
programmed through an SPI-compatible serial control port.
The AD1958 is fully compatible with all known DVD formats
including 96 kHz and 192 kHz sample frequencies and 24 bits.
It also is backwards-compatible by supporting 50 µs/15 µs
digital de-emphasis for “redbook” compact discs, as well as
de-emphasis at 32 kHz and 48 kHz sample rates.
The AD1958 has a simple but flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1958 can be configured in left-justified, I2S, right-justified,
or DSP serial-port-compatible modes. It can support 16, 20,
and 24 bits in all modes. The AD1958 accepts serial audio data
in MSB first, two’s-complement format, and operates from a
single 5 V power supply. It is fabricated on a single monolithic
integrated circuit and housed in a 28-lead SSOP package for
operation over the temperature range –40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
XIN XOUT MCLK
LOOP CLOCK
FILTERS OUTPUTS
23
CONTROL DATA
INPUT
3
AD1958
OSC
PLL
CIRCUIT
SERIAL CONTROL
INTERFACE
VOLTAGE
REFERENCE
16-/20-/24-
BIT DIGITAL
DATA INPUT
3
SERIAL
DATA
INTERFACE
ATTEN/MUTE
ATTEN/MUTE
8 ؋ fS
INTERPOLATOR
8 ؋ fS
INTERPOLATOR
MULTIBIT
SIGMA-DELTA
MODULATOR
MULTIBIT
SIGMA-DELTA
MODULATOR
DAC
DAC
OUTPUT
BUFFER
OUTPUT
BUFFER
L
ANALOG
OUTPUTS
R
REV. 0
RESET MUTE ZERO FLAG
2
PLL SUPPLY
2
DIGITAL SUPPLY
3
ANALOG SUPPLY
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
AD1958
PIN FUNCTION DESCRIPTIONS
Pin Input/Output Mnemonic
1I
CCLK
2I
3I
CLATCH
RESET
4I
5I
6I
7I
8I
9O
10 O
11 O
12 I/O
13 O
14 I
15
16
17
18
19
20 O
21 O
22 I
23 O
24
25
26 O
27 I
28 I
LRCLK
BCLK
SDATA
DVDD
DGND
SCLK0
SCLK1
SCLK2
MCLK
XOUT
XIN
PVDD
PGND
LF0
LF1
AGND0
OUTR
FILTR
AGND1
OUTL
AVDD
FILTB
ZERO
MUTE
CDATA
Description
Control Clock Input for Control Data. Control input data must be valid on
the rising edge of CCLK. CCLK may be continuous or gated.
Latch Input for Control Data
Reset. The AD1958 is placed in a reset mode when this pin is held LO.
The serial control port registers are reset to their default values. Set HI for
normal operation.
Left/Right Clock Input for Input Data. Must run continuously.
Bit Clock Input for Input Data. Need not run continuously; may be gated
or used in a burst fashion.
Serial input, MSB first, containing two channels of 16/20/24 bits of two’s-
complement data per channel.
Digital Power Supply Connect to Digital 5 V Supply
Digital Ground
33.8688 MHz Clock Output
256/384/512/768 fS Output
16.9344 MHz/22.5792 MHz/512 fS Output
27 MHz Master Clock Output/256 fS DAC Clock Input
27 MHz Crystal Oscillator Output
27 MHz Crystal Oscillator/External Clock Input
PLL Power Supply. Connect to PLL 5 V Supply.
PLL Ground
PLL0 Loop Filter
PLL1 Loop Filter
Analog Ground
Right Channel Positive Line Level Analog Output
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND.
Analog Ground
Left Channel Line Level Analog Output
Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection. Connect 10 µF Capacitor to AGND.
Zero Flag Output. This pin goes HI when both channels have zero signal
input for more than 1024 L/R Clock Cycles.
Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for
normal operation.
Serial Control Input, MSB first, containing 16 bits of unsigned data
per channel. Used for specifying channel-specific attenuation and mute.
FUNCTIONAL DESCRIPTION
DAC
The AD1958 has two DAC channels arranged as a stereo pair
with single-ended analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 16384
linear steps. Digital inputs are supplied through a serial data
input pin, SDATA, a frame clock, LRCLK, and a bit clock, BLCK.
Each analog output pin sits at a dc level of VREF (present at
FILTR), and swings ± 1.585 V for a 0 dB digital input signal.
A single op amp third-order external low-pass filter is recom-
mended to remove high-frequency noise present on the output
pins. The output phase can be changed in an SPI control
register to accommodate inverting and noninverting filters.
Note that the use of op amps with low slew rate or low band-
width may cause high frequency noise and tones to fold down
into the audio band; care should be exercised in selecting
these components.
The FILTB and FILTR pins should be bypassed by external
capacitors to ground. The FILTB pin is used to reduce the noise
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the VREF pin, FILTR (VREF ~ 2.39 V)
can be used to bias external op amps used to filter the output signals.
The DAC master clock frequency is 256 fS for the 32 kHz–48 kHz
range (8ϫ interpolation, see Table I). For the 96 kHz range (4ϫ
interpolation) this is 128 fS. At 192 kHz (2ϫ interpolation), this
is 64 fS. It is supplied internally from the PLL clock system when
MCLK mode is set to Output in the PLL Control Register.
When the MCLK mode is changed to Input, it must be supplied
from an external source connected to MCLK. The output from
the 27 MHz PLL clock is disabled in this case.
REV. 0
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD1958.PDF ] | |
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