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AD1955 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1955
Beschreibung High Performance Multibit DAC with SACD Playback
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 10 Seiten
AD1955 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
a
High Performance Multibit Σ∆ DAC
with SACD Playback
Preliminary Technical Data
AD1955
FEATURES
5V Power Supply Stereo Audio DAC System.
Accepts 16/18/20/24-Bit Data
Supports 24-Bits, 192kHz Sample Rate PCM Audio Data
Supports SACD bit-stream and External Digital Filter Interface
Accepts a Wide Range of PCM Sample Rates Including:
32kHz, 44.1kHz. 48kHz, 88.2kHz, 96kHz, and 192kHz
Multibit Sigma Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and Noise Floor
Data Directed Scrambling DAC - Least Sensitive to Jitter
Supports SACD playback with “Bit Expansion” filter
Differential Current Output for Optimum Performance
8.64 mA p-p Output Current with +3dB headroom in SACD mode
120 dB SNR/DNR (not muted) at 48KHz Sample Rate
(A-Weighted Stereo)
123 dB SNR/DNR (Mono)
-110 dB THD+N
110 dB Stopband Attenuation with +/-0.0002dB Passband Ripple
8 Times Oversampling Digital Filter
On-chip Clickless Volume Control
Supports SACD-Mute pattern detection
Supports 64fs/128fs DSD SACD with phase modulation
Internal Digital Filter pass-through for External Filter
Master clock: 256fs,384fs,512fs,768fs
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-emphasis, Mono Mode
Digital De-emphasis for 32, 44.1, 48 KHz Sample Rates
Flexible Serial Data Port with Right-Justified, Left-Justified,
I2S-Compatible and DSP Serial Port
28 Lead SSOP Plastic Package
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
High-End DVD-Audio, SACD, CD, Home Theatre Systems, Automotive
Audio Systems, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1955 is a complete high performance single-chip stereo digital
audio playback system. It is comprised of a multibit sigma-delta
modulator, high performance digital interpolation filters, and continuous-
time differential current output DAC section. Other features include an
on-chip clickless stereo attenuator, mute capability, programmed through
an SPI-compatible serial control port. The AD1955 is fully compatible
with all known DVD audio formats including 192kHz as well as 96kHz
sample frequencies and 24-bits. It also is backwards compatible by
supporting 50/15µs digital de-emphasis intended for “redbook” Compact
Discs, as well as de-emphasis at 32kHz and 48kHz sample rate.
The AD1955 has a very flexible serial data input port that allows for
glueless interconnection to a variety of ADCs, DSPs, SACD decoder,
external digital filter, AES/EBU receivers and sample rate converters.
The AD1955 can be configured in Left-justified, I2S, Right-Justified, or
DSP serial port compatible modes. It can support MSB first, twos-
compliment format, 16, 18, 20 and 24 bits in all standard PCM modes.
Also the AD1955 has an interface for SACD playback and an external
digital filter interface for use with an external digital interpolation filter
or HDCD decoder. The AD1955 uses a +5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed in a 28-
pin SSOP package for operation over the temperature range -400C to
+1050C.
Master Clock
Input
Control Data
Input
3
Digital
Supply
16/20/24Bit
Audio Data /
External Digital
Filter Input
3/4
Auto-Clock
Divider
SPI
Control
Serial Data
Digital
M
U
Interface
Filter
Engine
X External
Filter I/F
Multibit
Sigma-Delta
S/H Modulator
Noise-
Shaped
Scrambling
Voltage
Reference
I-DAC
I-DAC
L-ch
Differential
Current Output
R-ch
DSD
Bitstream
Input
4
DSD
Filter
RESET
MUTE
Analog ZERO Flags
Supply
Rev. PrF 3/18/2002
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use;
nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
©Analog Devices, Inc., 2002






AD1955 Datasheet, Funktion
AD1955
PRELIMINARY TECHNICAL DATA
OPERATING FEATURES
Serial Data Input Port
The AD1955’s flexible serial data input port accepts standard PCM audio data and external digital filter output data in twos-
complement, MSB-first format in PCM/External digital filter mode and a dedicated SACD serial port accepts DSD bit-stream data in
SACD mode. If the PCM mode is selected by control register 0 bit12 and 13, the left channel data field always precedes the right
channel data field. The serial data format and word length in PCM mode are set by the mode select bits (bits 4 and 5 and bits 2 and 3,
respectively) in the SPI control register.
In all data formats except for the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra
bits will not cause an error, but they will be truncated internally). In Right-justified mode, control register 0, bits 2 and 3 are used to
set the word length to 16, 18, 20, or 24 bits. The default on power up is 24-bit, I2S.
In the external digital filter mode, selected by control register 0 bit 12 and 13, bits 2 and 3 are used to set the word length to 16, 18, 20
or 24 bits and the format is set with bits 4 and 5. For a burst-mode clock, the format should be set to Left-justified. DSP mode is not
used. The LRCLK is always falling-edge active. The default on power-up is 24-bit mode in PCM and external digital filter mode.
In SACD mode, selected by control register 0, bit 12 and 13, the SACD port will accept a DSD bit-stream.
When the SPI Control Port is not being used, the SPI pins (24, 25 and 26) should be tied to DGND or DVDD.
Serial Data Format in PCM mode
The supported formats are shown in Figure 1. For detailed timing, see Figure 2.
In Left-justified mode, LRCLK is HIGH for the left channel, and LOW for the right channel. Data should valid on the rising edge of
BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay.
In I2S mode, LRCLK is LOW for the left channel, and HIGH for the right channel. Data should be valid on the rising edge of BCLK.
The MSB is left-justified to an LRCLK transition but with a single BCLK period delay.
In DSP serial port mode, LRCLK must pulse HIGH for at least one bit clock period before the MSB of the left channel is valid, and
LRCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data should be valid on the
falling edge of BCLK. The DSP serial port mode can be used with any wordlength up to 24 bits.
In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse after RESET, and
that synchronism is maintained from that point forward.
In Right-justified mode (16 bits shown), LRCLK is HIGH for the left channel, LOW for the right channel. Data is valid on the rising
edge of BCLK.
In normal operation, there are 64 bit clocks per frame (or 32 per half-frame). When the SPI wordlength control bits (bits 2 and 3 in
control register 0) are set to 24 bits (0:0), the serial port will begin to accept data starting at the 8th bit clock pulse after the LRCLK
transition. When the word length control bits are set to 20-bit mode, data is accepted starting at the 12th bit clock position. In 18-bit
mode, data is accepted starting at the 14th bit clock position. In 16-bit mode, data is accepted starting at the 16th bit clock position.
These delays are independent of the number of bit clocks per frame, and therefore other data formats are possible using the delay
values described above.
Note that the AD1955 is capable of a 32 X Fs BCLK frequency “packed mode” where the MSB is left-justified to an LRCLK
transition, and the LSB is right-justified to the opposite LRCLK transition. LRCLK is HIGH for the left channel, and LOW for the
right channel. Data is valid on the rising edge of BLCK. Packed mode can be used when the AD1955 is programmed in left or right-
justified mode.
Serial Data Format in External Digital Filter mode
In the external digital filter mode, the AD1955 will accept up to 24 bits serial, twos compliment, MSB first data from an external
digital filter, an HDCD decoder or a general purpose DSP. If the external digital filter mode is selected by control register 0, bits 12
and 13, pins 2 to 5 are assigned as the word clock input (EF_WCLK, Pin 2) , bit clock input (EF_BCLK, Pin 3), left channel data input
(EF_LDATA, Pin 4) and right channel data input (EF_RDATA, Pin 5) respectively to accept 8fs (48 kHz), 4fs (96kHz) or 2fs (196
kHz) over-sampled data.
-6- Rev. PrF

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