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PDF AD1954 Data sheet ( Hoja de datos )
| Número de pieza | AD1954 | |
| Descripción | SigmaDSP 3-Channel/ 26-Bit Signal Processing DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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SigmaDSP™ 3-Channel, 26-Bit
Signal Processing DAC
AD1954
FEATURES
5 V 3-Channel Audio DAC System
Accepts Sample Rates up to 48 kHz
7 Biquad Filter Sections per Channel
Dual Dynamic Processor with Arbitrary Input/Output Curve
and Adjustable Time Constants
0 ms to 6 ms Variable Delay/Channel for Speaker Alignment
Stereo Spreading Algorithm for Phat Stereo™ Effect
Program RAM Allows Complete New Program Download
via SPI Port
Parameter RAM Allows Complete Control of More Than
200 Parameters via SPI Port
SPI Port Features Safe-Upload Mode for Transparent Filter
Updates
2 Control Registers Allow Complete Control of Modes and
Memory Transfers
Differential Output for Optimum Performance
112 dB Signal-to-Noise (Not Muted) at 48 kHz Sample Rate
(A-Weighted Stereo)
70 dB Stop-Band Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Digital De-emphasis Processing for 32 kHz, 44.1 kHz, and
48 kHz Sample Rates
Flexible Serial Data Port with Right-Justified, Left-Justified,
I2S Compatible, and DSP Serial Port Modes
Auxiliary Digital Input
Graphical Custom Programming Tools
44-Lead MQFP or 48-Lead LQFP Plastic Package
APPLICATIONS
2.0/2.1 Channel Audio Systems (Two Main Channels plus
Subwoofer)
Multimedia Audio
Automotive Sound Systems
Minicomponent Stereo
Home Theater Systems (AC-3 Postprocessor)
Musical Instruments
In-Seat Sound Systems (Aircraft, Motor Coaches)
GENERAL DESCRIPTION
The AD1954 is a complete 26-bit single-chip 3-channel digital
audio playback system with built-in DSP functionality for speaker
equalization, dual-band compression/limiting, delay compensa-
tion, and image enhancement. These algorithms can be used to
compensate for real-world limitations of speakers, amplifiers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1954 is comparable to that
found in high-end studio equipment. Most of the processing is
done in full 48-bit double-precision mode, resulting in very good
low-level signal performance and the absence of limit cycles or
idle tones. The compressor/limiter uses a sophisticated two-band
algorithm often found in high-end broadcast compressors.
(Continued on 9)
FUNCTIONAL BLOCK DIAGRAM
SERIAL DATA
OUTPUT
SERIAL DATA
INPUTS
MASTER CLOCK
OUTPUT
MASTER
CLOCK INPUTS
AUX SERIAL
DATA INPUT
SPI DATA
OUTPUT
SPI INPUT
3
3
3
3
3
AUDIO DATA
MUX
MCLK
MUX
MCLK
GENERATOR
(256fS/512fS)
SERIAL CONTROL
INTERFACE
26 22
DSP CORE
DATA FORMAT:
3.23 (SINGLE PRECISION)
3.45 (DOUBLE PRECISION)
AD1954
DAC – L
DAC – R
DAC – SW
RAM
ROM
DATA CAPTURE
OUT
ANALOG
OUTPUTS
DIGITAL
OUTPUT
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or other-
wise under any patent or patent rights of Analog Devices.Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
1 page  
DIGITAL TIMING
Parameter
tDMDC MCLK Recommended Duty Cycle @ 12.288 MHz (256 fS Mode)
tDMDC MCLK Recommended Duty Cycle @ 24.576 MHz (512 fS Mode)
tDMD MCLK Delay (All Mode)
tDBH BCLK Low Pulsewidth
tDBH BCLK High Pulsewidth
tDBD BCLK Delay (to BCLKO)
tDLS LRCLK Setup
tDLH LRCLK Hold
tDLD LRCLK Delay (to LRCLKO)
tDDS SDATA Setup
tDDH SDATA Hold
tDDD SDATA Delay (to SDATAO)
tCCL CCLK Low Pulsewidth
tCCH CCLK High Pulsewidth
tCLS CLATCH Setup
tCLH CLATCH Hold
tCLD CLATCH High Pulsewidth
tCDS CDATA Setup
tCDH CDATA Hold
tCOD COUT Delay
tCOH COUT Hold
tDCD DCSOUT Delay
tDCH DCSOUT Hold
tPDRP PD/RST Low Pulsewidth
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS AT 44.1 KHZ
Parameter
Pass-Band Ripple
Stop-Band Attenuation
Pass Band
Stop Band
Group Delay
Specifications subject to change without notice.
AD1954
Min Typ Max Unit
45 55 %
40 60 %
25 ns
10 ns
10 ns
25 ns
0 ns
10 ns
25 ns
0 ns
10 ns
25 ns
12 ns
12 ns
10 ns
10 ns
10 ns
0 ns
10 ns
35 ns
2 ns
35 ns
2 ns
5 ns
Min Typ
Max Unit
70
20
0.5442 fS
24
0.4535 fS
24.625/fS
±0.01
dB
dB
kHz
kHz
sec
REV. A
–5–
5 Page 
DCSOUT—Data Capture Serial Out
This pin will output the DSP’s internal signals, which can be used
by external DACs or other signal processing devices. The signals
that are captured and output on the DCSOUT pin are controlled
by writing program counter trap numbers to SPI Addresses 263
(for the left output) and 264 (for the right output).When the inter-
nal program counter contents are equal to the trap values written
to the SPI port, the selected DSP register is transferred to the
DCSOUT parallel-to-serial registers and shifted out on the
DCSOUT pin. Table XX shows the program counter trap values
and register-select values that should be used to tap various inter-
nal points of the algorithm flow.
The DCSOUT pin is meant to be used in conjunction with the
LRCLK and BCLK signals that are provided to the serial input
port. The format of DCSOUT is the same as the format used
for the serial port. In other words, if the serial port is running in
I2S mode, then the DCSOUT pin, together with the LRCLK0
and BCLK0 pins (assuming input 0 is selected), will form a valid
3-wire I2S output.
The DCSOUT pin can be used for a variety of purposes. If the
DCSOUT pin is used to drive another external DAC, then a
4.1 system is possible using a new program downloaded into the
program RAM.
DEEMP/SDATA_AUX—De-emphasis Input Pin/Auxiliary Serial
Data Input
In de-emphasis mode, if this pin is asserted high, then a digital
de-emphasis filter will be inserted into the signal flow. The
de-emphasis curve is valid only for a sample rate of 44.1 kHz;
curves for 32 kHz and 48 kHz may be programmed using the
SPI port.This pin can also be used as an auxiliary 2-channel serial
data input. This function is set by writing a 1 to Bit 11 of Control
Register 1. The same clocks are used for this serial input as are
used for the SDATA0, SDATA1, and SDATA2 signals. This serial
input can only be used in the signal processing flow when using
Analog Devices’ custom programming tools; see the Graphical
Custom Programming Tools section. The use of de-emphasis is
still available while this pin is used as a serial input but only
through SPI control.
MUTE—Mute Output Signal
When this pin is asserted high, a ramp sequence is started, which
gradually reduces the volume to zero.When de-asserted, the volume
ramps from zero back to the original volume setting.The ramp
speed is timed so that it takes 10 ms to reach 0 volume when starting
from the default 0 dB volume setting.
VOUTL+, VOUTL2—Left Channel Differential Analog Outputs
Full-scale outputs correspond to 1 Vrms on each output pin or
2 V rms differential, assuming a VREF input voltage of 2.5 V.
AD1954
The full-scale swing scales directly with VREF. These outputs are
capable of driving a load of >5 k, with a maximum peak current
of 1 mA from each pin. An external third order filter is recom-
mended for filtering out-of-band noise.
VOUTR+, VOUTR2 —Right Channel Differential Outputs
See characteristics for left channel VOUTL+,VOUTL–.
VOUTS+, VOUTS2 —Subchannel Differential Outputs
These outputs are designed to drive loads of 10 k or greater,
with a peak current capability of 250 µA. This output does not
use digital interpolation, since it is intended for low frequency
applications. An external third order filter with a cutoff frequency
<2 kHz is recommended.
VREF—Analog Reference Voltage Input
The nominal VREF input voltage is 2.5 V; the analog gain scales
directly with the voltage on this pin.When using the AD1954 to
drive a power amplifier, it is recommended that the VREF voltage
be derived by dividing down and heavily filtering the supply to the
power amplifier. This provides a benefit if the compressor/limiter
in the AD1954 is used to prevent amplifier clipping. In this case, if
the DAC output voltage is scaled to the amplifier power supply, a
fixed compressor threshold can be used to protect an amplifier
whose supply may vary over a wide range. Any ac signal on this
pin will cause distortion, and therefore, a large decoupling capaci-
tor may be necessary to ensure that the voltage on VREF is clean.
The input impedance of VREF is greater than 1 M.
FILTCAP—Filter Capacitor Point
This pin is used to reduce the noise on an internal biasing point
in order to provide the highest performance. It may not be neces-
sary to connect this pin, depending on the quality of the layout
and the grounding used in the application circuit.
DVDD—Digital VDD for Core
5 V nominal.
ODVDD—Digital VDD for All Digital Outputs
Variable from 2.7 V to 5.5 V.
DGND (2)—Digital Ground
AVDD (3)—Analog VDD
5 V nominal. For best results, use a separate regulator for AVDD.
Bypass capacitors should be placed close to the pins and connected
directly to the analog ground plane.
AGND (3)—Analog Ground
For best performance, separate nonoverlapping analog and digital
ground planes should be used.
REV. A
–11–
11 Page | ||
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