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PDF AD1953 Data sheet ( Hoja de datos )
| Número de pieza | AD1953 | |
| Descripción | SigmaDSP 3-Channel/ 26-Bit Signal Processing DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
SigmaDSP™ 3-Channel, 26-Bit
Signal Processing DAC
AD1953
FEATURES
5 V 3-Channel Audio DAC System
Digital Audio Output (2-Channel or 6-Channel
Packed Mode)
Accepts Sample Rates up to 48 kHz
7 Biquad Filter Sections per Channel
Dual Dynamic Processor with Arbitrary Input/Output
Curve and Adjustable Time Constants
0 ms to 6 ms Variable Delay/Channel for Speaker Alignment
Stereo Spreading Algorithm for Phat Stereo™ Effect
Program RAM Allows Complete New Program Download
via SPI Port
Parameter RAM Allows Complete Control of More Than
200 Parameters via SPI Port
SPI Port Features Safe-Upload Mode for Transparent
Filter Updates
2 Control Registers Allow Complete Control of Modes
and Memory Transfers
Differential Output for Optimum Performance
112 dB Signal-to-Noise (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
70 dB Stop-Band Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Digital De-emphasis Processing for 32 kHz, 44.1 kHz, 48 kHz
Sample Rates
APPLICATIONS
2.0/2.1 Channel Audio Systems (2 Main Channels
Plus Subwoofer)
Multichannel Automotive Sound Systems
Multimedia Audio
Mini Component Stereo
Home Theater Systems (AC-3 Postprocessor)
Musical Instruments
In-Seat Sound Systems (Aircraft, Motor Coaches)
PRODUCT OVERVIEW
The AD1953 is a complete 26-bit, single-chip, 3-channel digital
audio playback system with built-in DSP functionality for speaker
equalization, dual-band compression/limiting, delay compensa-
tion, and image enhancement. These algorithms can be used to
compensate for real-world limitations of speakers, amplifiers,
and listening environments, resulting in a dramatic improvement
of perceived audio quality.
The signal processing used in the AD1953 is comparable to that
found in high end studio equipment. Most of the processing is
done in full 48-bit double-precision mode, resulting in very good
low level signal performance and the absence of limit cycles or
idle tones. The compressor/limiter uses a sophisticated two-band
algorithm often found in high end broadcast compressors.
(continued on page 9)
Flexible Serial Data Port with Right-Justified, Left-Justified,
I2S Compatible, and DSP Serial Port Modes
Auxiliary Digital Input
Graphical Custom Programming Tools
48-Lead LQFP Plastic Package
FUNCTIONAL BLOCK DIAGRAM
SERIAL DATA
OUTPUT
SERIAL DATA
INPUTS
MASTER CLOCK
OUTPUT
MASTER
CLOCK INPUTS
3
3
3
3
AUDIO DATA
MUX
MCLK
MUX
MCLK
GENERATOR
(256/512 fS)
26 ؋ 22
DSP CORE
DATA FORMAT:
3.23 (SINGLE PRECISION)
3.45 (DOUBLE PRECISION)
AD1953
DAC – L
DAC – R
DAC – SW
ANALOG
OUTPUTS
AUX SERIAL
DATA INPUT
SPI DATA
OUTPUT
SPI INPUT
3
SERIAL CONTROL
INTERFACE
RAM
ROM
DATA CAPTURE
OUT/TDM OUT
DIGITAL
OUTPUT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
DIGITAL TIMING
Parameter
tDMD
tDMD
tDMD
tDBH
tDBH
tDBD
tDLS
tDLH
tDLD
tDDS
tDDH
tDDD
tTFS
tTBS
tTOS
tCCL
tCCH
tCLS
tCLH
tCLD
tCDS
tCDH
tCOD
tCOH
tDCD
tDCH
tPDRP
MCLK Recommended Duty Cycle @ 12.288 MHz (256 fS Mode)
MCLK Recommended Duty Cycle @ 24.576 MHz (512 fS Mode)
MCLK Delay (All Mode)
BCLK Low Pulsewidth
BCLK High Pulsewidth
BCLK Delay (to BCLKO)
LRCLK Setup
LRCLK Hold
LRCLK Delay (to LRCLKO)
SDATA Setup
SDATA Hold
SDATA Delay (to SDATAO)
TDMFS Delay (from MCLK)
TDMBC Delay (from MCLK)
TDMO Delay (from TDMBC)
CCLK Low Pulsewidth
CCLK High Pulsewidth
CLATCH Setup
CLATCH Hold
CLATCH High Pulsewidth
CDATA Setup
CDATA Hold
COUT Delay
COUT Hold
DCSOUT Delay
DCSOUT Hold
PD/RST Low Pulsewidth
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS at 44.1 kHz
Parameter
Pass-Band Ripple
Stop-Band Attenuation
Pass Band
Stop Band
Group Delay
Specifications subject to change without notice.
AD1953
Min
Typ
Max
Unit
45 55 %
40 60 %
25 ns
10 ns
10 ns
25 ns
0 ns
10 ns
25 ns
0 ns
10 ns
25 ns
35 ns
35 ns
5 ns
12 ns
12 ns
10 ns
10 ns
10 ns
0 ns
10 ns
35 ns
2 ns
35 ns
2 ns
5 ns
Min
Typ
Max
Unit
± 0.01
70
20
0.4535 ϫ fS
24
0.5442 ϫ fS
24.625/fS
dB
dB
kHz
kHz
sec
REV. 0
–5–
5 Page 
AD1953
shifted out on the DCSOUT pin. Table XXI shows the Pro-
gram Counter Trap values and register-select values that should
be used to tap various internal points of the algorithm flow.
The DCSOUT pin is meant to be used in conjunction with the
LRCLK and BCLK signals that are provided to the serial input
port. The format of DCSOUT is the same as the format used
for the serial port. In other words, if the serial port is running in
I2S mode, then the DCSOUT pin, together with the LRCLK0
and BCLK0 pins (assuming input 0 is selected), will form a
valid 3-wire I2S output.
The DCSOUT pin can be used for a variety of purposes. If the
DCSOUT pin is used to drive another external DAC, then a 4.1
system is possible using a new program downloaded into the
program RAM.
AUXDATA—Auxiliary Serial Data Input.
The AUXDATA pin may be used in conjunction with a custom
program to access two extra channels of serial input data, allow-
ing for a total of four input channels. The serial format is identical
to the selected format of SDATA0, 1, 2. The AUXDATA pin is
synchronous to the selected LRCLK and BCLK signal, and there-
fore should have the same timing as the main serial input signal.
MUTE—Mute Output Signal.
When this pin is asserted HIGH, a ramp sequence is started that
gradually reduces the volume to zero. When deasserted, the
volume ramps from zero back to the original volume setting.
The ramp speed is timed so that it takes 10 ms to reach zero
volume when starting from the default 0 dB volume setting.
VOUTL+, VOUTL– —Left-Channel Differential Analog Out-
puts. Full-scale outputs correspond to 1 V rms on each output pin,
or 2 V rms differential, assuming a VREF input voltage of 2.5 V. The
full-scale swing scales directly with VREF. These outputs are
capable of driving a load of > 5 kΩ, with a maximum peak current
of 1 mA from each pin. An external third-order filter is recom-
mended for filtering out-of-band noise.
VOUTR+, VOUTR– —Right Channel Differential Outputs.
Output characteristics are the same as for VOUTL+ and VOUTL–.
VOUTS+, VOUTS– —Sub Channel Differential Outputs.
These outputs are designed to drive loads of 10 kΩ or greater,
with a peak current capability of 250 µA. This output does not
use digital interpolation, as it is intended for low frequency
application. An external third-order filter with a cutoff frequency
< 2 kHz is recommended.
VREF—Analog Reference Voltage Input.
The nominal VREF input voltage is 2.5 V; the analog gain
scales directly with the voltage on this pin. When using the
AD1953 to drive a power amplifier, it is recommended that the
VREF voltage be derived by dividing down and heavily filtering
the supply to the power amplifier. This provides a benefit if the
compressor/limiter in the AD1953 is used to prevent amplifier
clipping. In this case, if the DAC output voltage is scaled to the
amplifier power supply, a fixed compressor threshold can be
used to protect an amplifier whose supply may vary over a wide
range. Any ac signal on this pin will cause distortion, and a large
decoupling capacitor may therefore be necessary to ensure that
the voltage on VREF is clean. The input impedance of VREF is
greater than 1 MΩ.
FILTCAP—Filter Capacitor Point.
This pin is used to reduce the noise on an internal biasing point
in order to provide the highest performance. It may not be nec-
essary to connect this pin, depending on the quality of the layout
and grounding used in the application circuit.
DVDD—Digital VDD for Core.
5 V nominal.
ODVDD—Digital VDD for All Digital Outputs.
Variable from 2.7 V to 5.5 V.
DGND (2)—Digital Ground.
AVDD (3)—Analog VDD.
5 V nominal. For best results, use a separate regulator for AVDD.
Bypass capacitors should be placed close to the pins and con-
nected directly to the analog ground plane.
AGND (3)—Analog Ground.
For best performance, separate nonoverlapping analog and
digital ground planes should be used.
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD1953.PDF ] | |
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