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AD1895 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1895
Beschreibung 192 kHz Stereo Asynchronous Sample Rate Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD1895 Datasheet, Funktion
a
192 kHz Stereo Asynchronous
Sample Rate Converter
AD1895*
FEATURES
Automatically Senses Sample Frequencies
No Programming Required
Attenuates Sample Clock Jitter
3.3 V–5 V Input and 3.3 V Core Supply Voltages
Accepts 16-/18-/20-/24-Bit Data
Up to 192 kHz Sample Rate
Input/Output Sample Ratios from 7.75:1 to 1:8
Bypass Mode
Multiple AD1895 TDM Daisy-Chain Mode
128 dB Signal-to-Noise and Dynamic Range
(A-Weighted, 20 Hz–20 kHz BW)
Up to –122 dB THD + N
Linear Phase FIR Filter
Hardware Controllable Soft Mute
Supports 256 ؋ fS, 512 ؋ fS or 768 ؋ fS Master Mode
Clock
Flexible Three-Wire Serial Data Port with Left-Justified,
I2S, Right-Justified (16-, 18-, 20-, 24-Bits), and TDM
Serial Port Modes
Master/Slave Input and Output Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Home Theater Systems, Automotive Audio Systems,
DVD, DVD-R, CD-R, Set-Top Boxes, Digital Audio
Effects Processors
PRODUCT OVERVIEW
The AD1895 is a 24-bit, high-performance, single-chip, second-
generation asynchronous sample rate converter. Based upon
Analog Devices, Inc. experience with its first asynchronous
sample rate converter, the AD1890, the AD1895 offers improved
performance and additional features. This improved performance
includes a THD + N range of –115 dB to –122 dB depending
on sample rate and input frequency, 128 dB (A-Weighted)
dynamic range, 192 kHz sampling frequencies for both input and
output sample rates, improved jitter rejection, and 1:8 upsampling
and 7.75:1 downsampling ratios. Additional features include
more serial formats, a bypass mode, and better interfacing to
digital signal processors.
The AD1895 has a 3-wire interface for the serial input and
output ports that supports left-justified, I2S, and right-justified
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output
port supports TDM mode for daisy chaining multiple AD1895s to
FUNCTIONAL BLOCK DIAGRAM
RESET VDD_IO VDD_CORE
MUTE_I
SDATA_I
SCLK_I
LRCLK_I
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
BYPASS
MUTE_O
SERIAL
INPUT
FIFO
DIGITAL
PLL
AD1895
FSOUT
FSIN
FIR
FILTER
SERIAL
OUTPUT
SDATA_O
SCLK_O
LRCLK_O
TDM_IN
SMODE_O_0
SMODE_O_1
CLOCK DIVIDER
ROM
WLNGTH_O_0
WLNGTH_O_1
MCLK_I MSMODE_0 MSMODE_2
MCLK_O MSMODE_1
a digital signal processor. The serial output data is dithered down
to 20, 18 or 16 bits when 20-, 18- or 16-bit output data is selected.
The AD1895 sample rate converts the data from the serial input
port to the sample rate of the serial output port. The sample rate
at the serial input port can be asynchronous with respect to the
output sample rate of the output serial port. The master clock to
the AD1895, MCLK, can be asynchronous to both the serial
input and output ports.
MCLK can either be generated off-chip or on-chip by the AD1895
master clock oscillator. Since MCLK can be asynchronous to the
input or output serial ports, a crystal can be used to generate
MCLK internally to reduce noise and EMI emissions on the
board. When MCLK is synchronous to either the output or input
serial port, the AD1895 can be configured in a master mode where
MCLK is divided down and used to generate the left/right
and bit clocks for the serial port that is synchronous to MCLK.
The AD1895 supports master modes of 256 × fS, 512 × fS, and
768 × fS for both input and output serial ports.
Conceptually, the AD1895 interpolates the serial input data by
a rate of 220 and samples the interpolated data stream by the
output sample rate. In practice, a 64-tap FIR filter with 220
polyphases, a FIFO, a digital servo loop that measures the time
difference between input and output samples within 5 ps, and a
digital circuit to track the sample rate ratio are used to perform
the interpolation and output sampling. Refer to the Theory of
Operation section. The digital servo loop and sample rate ratio
circuit automatically track the input and output sample rates.
*Patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
(Continued on page 15)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






AD1895 Datasheet, Funktion
AD1895
PIN FUNCTION DESCRIPTIONS
Pin No. IN/OUT
Mnemonic
1 IN
NC
2 IN
MCLK_IN
3 OUT
MCLK_OUT
4 IN
SDATA_I
5
IN/OUT
SCLK_I
6
IN/OUT
LRCLK_I
7 IN
VDD_IO
8 IN
DGND
9 IN
BYPASS
10 IN
SMODE_IN_0
11 IN
SMODE_IN_1
12 IN
13 IN
SMODE_IN_2
RESET
14 IN
MUTE_IN
15 OUT
MUTE_OUT
16 IN
WLNGTH_OUT_1
17 IN
WLNGTH_OUT_0
18 IN
SMODE_OUT_1
19 IN
SMODE_OUT_0
20 IN
TDM_IN
21 IN
DGND
22 IN
VDD_CORE
23 OUT
SDATA_O
24
IN/OUT
LRCLK_O
25
IN/OUT
SCLK_O
26 IN
MMODE_0
27 IN
MMODE_1
28 IN
MMODE_2
*Also used to input matched-phase mode data.
Description
No Connect
Master Clock or Crystal Input
Master Clock Output or Crystal Output
Input Serial Data (at Input Sample Rate)
Master/Slave Input Serial Bit Clock
Master/Slave Input Left/Right Clock
3.3 V/5 V Input/Output Digital Supply Pin
Digital Ground Pin
ASRC Bypass Mode, Active High
Input Port Serial Interface Mode Select Pin 0
Input Port Serial Interface Mode Select Pin 1
Input Port Serial Interface Mode Select Pin 2
Reset Pin, Active Low
Mute Input Pin— Active HI Normally Connected to MUTE_OUT
Output Mute Control – Active HI
Hardware Selectable Output Wordlength—Select Pin 1
Hardware Selectable Output Wordlength—Select Pin 0
Output Port Serial Interface Mode Select Pin 1
Output Port Serial Interface Mode Select Pin 0
Serial Data Input* (Only for Daisy-Chain Mode). Ground when not used.
Digital Ground Pin
3.3 V Digital Supply Pin
Output Serial Data (at Output Sample Rate)
Master/Slave Output Left/Right Clock
Master/Slave Output Serial Bit Clock
Master/Slave Clock Ratio Mode Select Pin 0
Master/Slave Clock Ratio Mode Select Pin 1
Master/Slave Clock Ratio Mode Select Pin 2
PIN CONFIGURATION
NC 1
28 MMODE_2
MCLK_IN 2
27 MMODE_1
MCLK_OUT 3
26 MMODE_0
SDATA_I 4
AD1895
25 SCLK_O
SCLK_I
5
TOP VIEW
(NOT TO SCALE)
24 LRCLK_O
LRCLK_I 6
23 SDATA_O
VDD_IO 7
22 VDD_CORE
DGND 8
21 DGND
BYPASS 9
20 TDM_IN
SMODE_IN_0 10
19 SMODE_OUT_0
SMODE_IN_1 11
18 SMODE_OUT_1
SMODE_IN_2 12
17 WLNGTH_OUT_0
RESET 13
16 WLNGTH_OUT_1
MUTE_IN 14
15 MUTE_OUT
NC = NO CONNECT
–6– REV. A

6 Page









AD1895 pdf, datenblatt
AD1895
119
121
123
125
127
129
131
133
135
30000
55000
80000 105000 130000 155000 180000
OUTPUT SAMPLE RATE Hz
TPC 31. DNR vs. Output Sample Rate, fS_IN = 96 kHz,
–60 dBFS 1 kHz Tone
5
15
192 kHz:96 kHz
35
55 192 kHz:48 kHz
75
192 kHz:32 kHz
95
115
135
0
10000
20000 30000 40000
FREQUENCY Hz
50000
60000
TPC 32. Digital Filter Frequency Response
119
121
123
125
127
129
131
133
135
30000
55000
80000 105000 130000 155000 180000
OUTPUT SAMPLE RATE Hz
TPC 33. DNR vs. Output Sample Rate, fS_IN = 48 kHz,
–60 dBFS 1 kHz Tone
119
121
123
125
127
129
131
133
135
30000
55000
80000 105000 130000 155000 180000
OUTPUT SAMPLE RATE Hz
TPC 34. DNR vs. Output Sample Rate, fS_IN = 44.1 kHz,
–60 dBFS 1 kHz Tone
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0
4000
8000 12000 16000
FREQUENCY Hz
20000
24000
TPC 35. Passband Ripple, 192 kHz:48 kHz
5
4
3
2
1
0
1
2
3
4
5
140
120
100 80 60 40
INPUT LEVEL dBFS
20
0
TPC 36. Linearity Error, 48 kHz:48 kHz, 0 dBFS to
–140 dBFS Input, 200 Hz Tone
–12–
REV. A

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