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PDF AD1893 Data sheet ( Hoja de datos )
| Número de pieza | AD1893 | |
| Descripción | Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter | |
| Fabricantes | Analog Devices | |
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a
Low Cost SamplePort®
16-Bit Stereo Asynchronous
Sample Rate Converter
AD1893
FEATURES
Low Cost
LQFP and PDIP Packages
3 V Supply Performance Specified—Very Low Power
Automatically Senses Sample Frequencies—No
Programming Required
Rejects Sample Clock Jitter
Accommodates Dynamically Changing Asynchronous
Sample Clocks
8 kHz to 56 kHz Sample Clock Frequency Range
Approximately 1:2 to 2:1 Ratio Between Sample
Clocks
–96 dB THD+N at 1 kHz
96 dB Dynamic Range
Optimal Clock Tracking Control—Slow/Fast Settling
Modes
Linear Phase in All Modes
Automatic Output Mute
Flexible Four-Wire Serial Interfaces with Right-Justified
Mode
Power-Down Mode
On-Chip Oscillator
APPLICATIONS
Consumer CD-R, DAT, DCC, MD and 8 mm Video Tape
Recorders Including Portables
Digital Audio Communication/Network Systems
Computer Multimedia Systems
PRODUCT OVERVIEW
The AD1893 SamplePort is a fully digital, stereo Asynchronous
Sample Rate Converter (ASRC) that solves sample rate interfacing
and compatibility problems in digital audio equipment. Concep-
tually, this converter interpolates the input data up to a very high
internal sample rate with a time resolution of 300 ps, then deci-
mates down to the desired output sample rate. The AD1893 is
intended for 16-bit low cost, non-varispeed applications where low
voltage, low power (i.e., battery-powered) operation is required.
Refer to the AD1890/AD1891 data sheet for other products in the
SamplePort family. This device is asynchronous because the fre-
quency and phase relationships between the input and output
sample clocks (both are inputs to the AD1893 ASRC) are arbitrary
and need not be related by a simple integer ratio. There is no need
to explicitly select or program the input and output sample clock
frequencies, as the AD1893 automatically senses the relationship
between the two clocks. The input and output sample clock fre-
quencies can nominally range from 8 kHz to 56 kHz, and the ratio
between them can vary from approximately 1:2 to 2:1.
SamplePort is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
SYSTEM DIAGRAM
EXAMPLE
FREQUENCIES:
DAT 48kHz OR
CD 44.1kHz OR
BROADCAST 32kHz
INPUT SAMPLE CLOCK
INPUT SERIAL DATA
AD1893
EXAMPLE
FREQUENCIES:
DAT 48kHz OR
CD 44.1kHz OR
BROADCAST 32kHz
OUTPUT SAMPLE CLOCK
OUTPUT SERIAL DATA
The AD1893 uses multirate digital signal processing techniques
to construct an output sample stream from the input sample
stream. The input word width is 4 to 16 bits for the AD1893.
Shorter input words are automatically zero-filled in the LSBs.
The output word width is 24 bits. The user can receive as many
of the output bits as desired. Internal arithmetic is performed
with 22-bit coefficients and 27-bit accumulation. The digital
samples are processed with unity gain.
The input and output control signals allow for considerable
flexibility for interfacing to a variety of DSP chips, AES/EBU
receivers and transmitters and for I2S compatible devices. Input
and output data can be independently right- or left- (with or
without a one bit clock delay) justified to the left/right clock
edge. In the right-justified mode, the MSB is delayed 16-bit
clock periods from the left/right clock edge transition. Input and
output data can also be independently justified to the word
clock rising edge. The data justification options are encoded on
two mode pins for both the input port and the output port. The
bit clocks can also be independently configured for rising edge
active or falling edge active operation.
The AD1893 SamplePort ASRC has on-chip digital coefficients
that correspond to a highly oversampled 0 Hz to 20 kHz low-
pass filter with a flat passband, a very narrow transition band,
and a high degree of stopband attenuation. A subset of these
filter coefficients are dynamically chosen on the basis of the
filtered ratio between the input sample clock (LR_I) and the
output sample clock (LR_O), and these coefficients are then
used in an FIR convolver to perform the sample rate conversion.
Refer to the Theory of Operation section of this data sheet for a
more thorough functional description. The low-pass filter has
been designed so that full 20 kHz bandwidth is maintained
when the input and output sample clock frequencies are as low
as 44.1 kHz. If the output sample rate drops below the input
sample rate, the bandwidth of the input signal is automatically
(continued on Page 4)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
AD1893
PIN CONFIGURATIONS
DIP
LQFP
XTAL_O 1
XTAL_I 2
SERIAL IN
28 SETSLW
27 PWRDWN
DATA_I 3
BCLK_I 4
WCLK_I 5
LR_I 6
VDD
GND
7
8
NC 9
BKPOL_I 10
MODE0_I 11
MODE1_I 12
SERIAL OUT
ACCUM
MULT
FIFO
COEF ROM
26 BCLK_O
25 WCLK_O
24 LR_O
23 DATA_O
22 VDD
21 GND
20 NC
19 BKPOL_O
18 MODE0_O
17 MODE1_O
NC 1
BCLK_I 2
WCLK_I 3
LR_I 4
NC 5
VDD 6
GND 7
NC 8
BKPOL_I 9
MODE0_I 10
NC 11
44 43 42 41 40 39 38 37 36 35 34
AD1893
SERIAL IN
SERIAL OUT
ACCUM
MULT
FIFO
COEF ROM
CLOCK
TRACKING
33 NC
32 WCLK_O
31 LR_O
30 DATA_O
29 NC
28 VDD
27 GND
26 NC
25 BKPOL_O
24 MODE0_O
23 NC
RESET 13
GND 14
CLOCK
TRACKING
NC = NO CONNECT
AD1893 PIN LIST
AD1893
16 MUTE_O
15 MUTE_I
12 13 14 15 16 17 18 19 20 21 22
NC = NO CONNECT
Serial Input Interface
Pin Name DIP LQFP I/O Description
DATA_I 3
BCLK_I 4
WCLK_I 5
LR_I
6
43 I Serial input, MSB first, containing two channels of 4 to 16 bits of twos-complement data per
channel.
2 I Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion.
3 I Word clock input for input data. This input is rising edge sensitive. (Not required in LR input
data clock triggered modes.)
4 I Left/right clock input for input data. Must run continuously.
Serial Output Interface
Pin Name DIP LQFP I/O Description
DATA_O 23 30
O Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per
channel.
BCLK_O 26
WCLK_O 25
LR_O
24
35
32
31
I Bit clock input for output data. Need not run continuously; may be gated or used in a burst
fashion.
I Word clock input for output data. This input is rising edge sensitive. (Not required in LR output
data clock triggered modes.)
I Left/right clock input for output data. Must run continuously.
Input Control Signals
Pin Name DIP LQFP I/O Description
BKPOL_I 10 9
I Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI:
Inverted mode. Input data is sampled on falling edges of BCLK_I.
MODE0_I 11 10
I Serial mode zero control for input port.
MODE1_I 12 13
I Serial mode one control for input port.
MODE0_I
0
0
1
MODE1_I
0 Left-justified, no MSB delay, LR_I clock triggered.
1 Left-justified, MSB delay, LR_I clock triggered.
0 Right-justified, MSB delayed 16 bit clock periods from LR_I transition.
1 1 WCLK_I triggered, no MSB delay.
REV. A
–5–
5 Page 
AD1893
Sample Clock Jitter Rejection
The loop filter settling time also affects the ability of the
AD1893 ASRC to reject sample clock jitter, since the control
loop effectively computes a time weighted average or “esti-
mated” new output of many past input and output clock events.
This first order low pass filtering of the sample clock ratio pro-
vides the AD1893 with its jitter rejection characteristic. In the
slow settling mode, the AD1893 attenuates jitter frequencies
higher than 3 Hz (≈800 ms for the control loop to settle to an
18-bit “pure” sine wave), and thus rejects all but the most se-
vere sample clock jitter; performance is essentially limited only
by the FIR filter. In the fast settling mode, the ASRC attenuates
jitter components above 12 Hz (≈200 ms for the control loop to
settle). Due to the effects of on-chip synchronization of the
sample clocks to the 16 MHz (62.5 ns) crystal master clock,
sample clock jitter must be a large percentage of the crystal
period (>10 ns) before performance degrades in either the slow
or fast settling modes. Note that since both past input and past
output clocks are used to compute the filtered “current” internal
output clock request, jitter on both the input sample clock and
the output sample clock is rejected equally. In summary: the fast-
settling mode is best for applications when the sample rates will
be dynamically altered (e.g., varispeed situations), while the
slow-settling mode provides the most sample clock jitter rejection.
Clock jitter can be modeled as a frequency modulation process.
Figure 7 shows one such model, where a noise source combined
with a sine wave source modulates the “carrier” frequency gen-
erated by a voltage controlled oscillator.
NOISE SOURCE
NOISE
WAVEFORM
SINE
WAVE
VOLTAGE
SOURCE
Σ VCO
ANALOG IN
ADC
DIGITAL
OUT
Figure 7. Clock Jitter Modeled as a Modulated VCO
If the jittered output of the VCO is used to clock an analog-to-
digital converter, the digital output of the ADC will be contami-
nated by the presence of jitter. If the noise source is spectrally
flat (i.e., “white” jitter), an FFT of the ADC digital output
would show a spectrum with a uniform noise floor that is
elevated compared to the spectrum with the noise source turned
off. If the noise source has distinct frequency components (i.e.,
“correlated” jitter), then an FFT of the ADC digital output
would show symmetrical sidebands around the ADC input
signal, at amplitudes and frequencies determined by frequency
modulation theory. One notable result is that the level of the
noise or the sidebands is proportional to the slope of the input
signal, i.e., the worst case occurs at the highest frequency full-
scale input (a full-scale 20 kHz sinusoid).
The AD1893 applies rejection to these jitter frequency compo-
nents referenced to the input signal. In other words, if a 5 kHz
digital sinusoid is applied to the ASRC, depending on the set-
tling mode selected, the ASRC will attenuate sample clock jitter
at either 3 Hz above and below 5 kHz (slow settling) or 12 Hz
above and below 5 kHz (fast settling). The rolloff is 6 dB per
octave. As an example, suppose there was correlated jitter
present on the input sample clock with a 1 kHz component,
associated with the same 5 kHz sinusoidal input data. This
would produce sidebands at 4 kHz and 6 kHz, 3 kHz and
7 kHz, etc., with amplitudes that decrease as they move away
from the input signal frequency. For the slow-settling mode
case, 1 kHz represents more than nine octaves (relative to
3 Hz), so the first two sideband pairs would be attenuated by
more than 54 dB. For the fast-settling mode case, 1 kHz repre-
sents more than seven octaves (relative to 12 Hz), so that the
first two sideband pairs would be attenuated by more than 42 dB.
The second and higher sideband pairs are attenuated even more
because they are spaced further from the input signal frequency.
Group Delay Modes
The other parameter that determines the likelihood of FIFO
input overflow or output underflow is the FIFO depth. This
FIFO induced group delay is better termed transport delay,
since it is frequency independent, and should be kept conceptu-
ally distinct from the notion of group delay as used in the poly-
phase filter bank model. The total group delay of the AD1893
equals the FIFO transport delay plus the FIR (polyphase) filter
group delay.
In the AD1893, the FIFO read and write pointers are separated
by five memory locations (≈100 µs equivalent transport delay at
a 50 kHz sample rate). This is added to the FIR filter delay
(64 taps divided by 2) for a total nominal group delay in short
mode of ≈700 µs.
This delay is deterministic and constant except when FSOUT
drops below FSIN which causes the number of FIR filter taps to
increase (see Cutoff Frequency Modification section). If the
FIFO read and write addresses cross, the MUTE_O signal will
be asserted. Note that under all conditions, both the highly
oversampled low-pass prototype and the polyphase subfilters of
the AD1893 ASRC possess a linear phase response.
REV. A
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD1893.PDF ] | |
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