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AD1891 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1891
Beschreibung SamplePort Stereo Asynchronous Sample Rate Converters
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD1891 Datasheet, Funktion
a
SamplePort Stereo Asynchronous
Sample Rate Converters
AD1890/AD1891
FEATURES
Automatically Sense Sample Frequencies—No
Programming Required
Tolerant of Sample Clock Jitter
Smooth Transition When Sample Clock Frequencies
Cross
Accommodate Dynamically Changing Asynchronous
Sample Clocks
8 kHz to 56 kHz Sample Clock Frequency Range
1:2 to 2:1 Ratio Between Sample Clocks
–106 dB THD+N at 1 kHz (AD1890)
120 dB Dynamic Range (AD1890)
Optimal Clock Tracking Control
–Short/Long Group Delay Modes
–Slow/Fast Settling Modes
Linear Phase in All Modes
Equivalent of 4 Million 22-Bit FIR Filter Coefficients
Stored On-Chip
Automatic Output Mute
Flexible Four Wire Serial Interfaces
Low Power
APPLICATIONS
Digital Mixing Consoles and Digital Audio Workstations
CD-R, DAT, DCC and MD Recorders
Multitrack Digital Audio and Video Tape Recorders
Studio to Transmitter Links
Digital Audio Signal Routers/Switches
Digital Audio Broadcast Equipment
High Quality D/A Converters
Digital Tape Recorder Varispeed Applications
Computer Communication and Multimedia Systems
PRODUCT OVERVIEW
The AD1890 and AD1891 SamplePorts™ are fully digital, stereo
Asynchronous Sample Rate Converters (ASRCs) that solve sample
rate interfacing and compatibility problems in digital audio equip-
ment. Conceptually, these converters interpolate the input data up
to a very high internal sample rate with a time resolution of 300 ps,
then decimate down to the desired output sample rate. The
AD1890 is intended for 18- and 20-bit professional applications,
and the AD1891 is intended for 16-bit lower cost applications
where large dynamic sample-rate changes are not encountered.
These devices are asynchronous because the frequency and phase
relationships between the input and output sample clocks (both are
inputs to the AD1890/AD1891 ASRCs) are arbitrary and need not
be related by a simple integer ratio. There is no need to explicitly
select or program the input and output sample clock frequencies, as
the AD1890/AD1891 automatically sense the relationship between
SamplePort and SamplePorts are trademarks of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
SYSTEM DIAGRAM
EXAMPLE
FREQUENCIES:
DAT 48kHz OR
CD 44.1kHz OR
BROADCAST 32kHz
INPUT SAMPLE CLOCK
AD1890/
AD1891
EXAMPLE
FREQUENCIES:
DAT 48kHz OR
CD 44.1kHz OR
BROADCAST 32kHz
OUTPUT SAMPLE CLOCK
INPUT SERIAL DATA
OUTPUT SERIAL DATA
the two clocks. The input and output sample clock frequencies
can nominally range from 8 kHz to 56 kHz, and the ratio
between them can vary from 1:2 to 2:1.
The AD1890/AD1891 use multirate digital signal processing
techniques to construct an output sample stream from the input
sample stream. The input word width is 4 to 20 bits for the
AD1890 or 4 to 16 bits for the AD1891. Shorter input words
are automatically zero-filled in the LSBs. The output word
width for both devices is 24 bits. The user can receive as many
of the output bits as desired. Internal arithmetic is performed
with 22-bit coefficients and 27-bit accumulation. The digital
samples are processed with unity gain.
The input and output control signals allow for considerable flex-
ibility for interfacing to a variety of DSP chips, AES/EBU
receivers and transmitters and for I2S compatible devices. Input
and output data can be independently justified to the left/right
clock edge, or delayed by one bit clock from the left/right clock
edge. Input and output data can also be independently justified
to the word clock rising edge or delayed by one bit clock from
the word clock rising edge. The bit clocks can also be indepen-
dently configured for rising edge active or falling edge active
operation.
The AD1890/AD1891 SamplePort™ ASRCs have on-chip digi-
tal coefficients that correspond to a highly oversampled 0 kHz to
20 kHz low-pass filter with a flat passband, a very narrow tran-
sition band, and a high degree of stopband attenuation. A subset
of these filter coefficients are dynamically chosen on the basis of
the filtered instantaneous ratio between the input sample clock
(LR_I) and the output sample clock (LR_O), and these coeffi-
cients are used in an FIR convolver to perform the sample rate
conversion. Refer to the “Theory of Operation” section of this
data sheet for a more thorough functional description. The low-
pass filter has been designed so that full 20 kHz bandwidth is
maintained when the input and output sample clock frequencies
are as low as 44.1 kHz. If the output sample rate drops below
the input sample rate, the bandwidth of the input signal is
(continued on Page 4)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD1891 Datasheet, Funktion
AD1890/AD1891
Output Control Signals
Pin Name Number I/O
BKPOL_O 19
I
TRGLR_O 18
I
MSBDLY_O 17
I
Description
Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed
on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on rising.
Trigger on LR_O. HI: Changes in LR_O indicate beginning1 of valid output data. LO: Rising
edge of WCLK_O indicates beginning of valid output data.
MSB delay. HI: Output data is delayed one BCLK_O after either LR_O (TRGLR_O = HI) or
WCLK_O (TRGLR_O = LO) indicates the beginning of valid output data. Included for I2S data
format compatibility. LO: No delay.
Miscellaneous
Pin Name Number I/O
GPDLYS 1
I
MCLK
2
RESET
13
MUTE_O 16
MUTE_I 15
SETLSLW 28
I
I
O
I
I
N/C 9, 20
Description
AD1890 ONLY: Group delay—short. HI: Short group delay mode (700 µs). More sensitive to
changes in sample rates (LR clocks). LO: Long group delay mode (3 ms). More tolerant of
sample rate changes. This signal may be asynchronous with respect to MCLK, and dynamically
changed, but is normally pulled up or pulled down on a static basis. AD1891: Short group delay
mode only; this pin is a N/C.
Master clock input. Nominally 16 MHz for sampling frequencies (FS, word rates) from 8 kHz to
56 kHz. Exact frequency is not critical, and does not need to be synchronized to any other clock
or possess low jitter.
Active LO reset. Set HI for normal chip operation.
Mute output. HI indicates that data is not currently valid due to read and write FIFO memory
pointer overlap. LO indicates normal operation.
Mute input. HI mutes the serial output to zeros (midscale). Normally connected to MUTE_O.
Reset LO for normal operation.
Settle slowly to changes in sample rates. HI: Slow-settling mode (800 ms). Less sensitive to
sample clock jitter. LO: Fast-settling mode (200 ms). Some narrow-band noise modulation may
result from jitter on LR clocks. This signal may be asynchronous with respect to MCLK, and
dynamically changed, but is normally pulled up or pulled down on a static basis.
No connect. Reserved. Do not connect.
Power Supply Connections
Pin Name Number I/O Description
VDD
GND
7, 22
I
8, 14, 21, 27 I
Positive digital voltage supply.
Digital ground. Pins 14 and 27 need not be decoupled.
NOTE
1The beginning of valid data will be delayed by one BCLK_O if MSBDEL _O is selected (Hl).
–6– REV. 0

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AD1891 pdf, datenblatt
AD1890/AD1891
Cutoff Frequency Modification
The final important operating concept of the ASRCs is the mod-
ification of the filter cutoff frequency when the output sample
rate (FSOUT) drops below the input sample rate (FSIN), i.e.,
during downsampling operation. The AD1890/AD1891 auto-
matically reduces the polyphase filter cutoff frequency under
this condition. This lowering of the cutoff frequency (i.e., the
reduction of the input signal bandwidth) is required to avoid
alias distortion. The AD1890/AD1891 SoundPorts take advan-
tage of the scaling property of the Fourier transform which can
be stated as follows: if the Fourier transform of f(t) is F(w), then
the Fourier transform of f(k × t) is F(w/k). This property can be
used to linearly compress the frequency response of the filter,
simply by multiplying the coefficient ROM addresses (shown in
Figure 6) by the ratio of FSOUT to FSIN whenever FSOUT is less
than FSIN. This scaling property works without spectral distor-
tion because the time scale of the interpolated signal is so dense
(300 ps resolution) with respect to the cutoff frequency that the
discrete-time representation is a close approximation to the con-
tinuous time function.
The cutoff frequency (–3 dB down) of the FIR filter during
downsampling is given by the following relation:
Downsampling Cutoff Frequency = (FSOUT/44.1 kHz) × 20 kHz
The AD1890/AD1891 frequency response compression circuit
includes a first order low-pass filter to smooth the filter cutoff
frequency selection during dynamic sample rate conditions.
This allows the ASRC to avoid objectionable clicking sounds
that would otherwise be imposed on the output while the loop
settles to a new sample rate ratio. Hysteresis is also applied to
the filter selection with approximately 300 Hz of cutoff fre-
quency “noise margin,” which limits the available selection of
cutoff frequencies to those falling on an approximately 300 Hz
frequency grid. Thus if a particular sample frequency ratio was
reached by sliding the output sample frequency up, it is possible
that a filter will be chosen with a cutoff frequency that could dif-
fer by as much as 300 Hz from the filter chosen when the same
sample frequency ratio was reached by sliding the output sample
frequency down. This is necessary to ensure that the filter selec-
tion is stable even with severely jittered input sample clocks.
Note that when the filter cutoff frequency is reduced, the transi-
tion band of the filter becomes narrower since the scaling prop-
erty affects all filter characteristics. The number of FIR filter
taps necessarily increases because there are now a smaller num-
ber of longer length polyphase filters. Nominally, when FSOUT is
greater than FSIN, the number of taps is 64. When FSOUT is less
than FSIN, the number of taps linearly increase to a maximum of
128 when the ratio of FSOUT, to FSIN equals 1:2. The number of
filter taps as a function of sample clock ratio is illustrated in Fig-
ure 8. The natural consequence of this increase in filter taps is
an increase in group delay.
When the AD1890/AD1891 output sample frequency is higher
than the input sample frequency (i.e., upsampling operation),
the cutoff frequency of the FIR polyphase filter can be greater
than 20 kHz. The cutoff frequency of the FIR filter during
upsampling is given by the following relation:
Upsampling Cutoff Frequency = (FSIN/44.1 kHz) × 20 kHz
Noise and Distortion Phenomena
There are three noise/distortion phenomena that limit the per-
formance of the AD1890/AD1891 ASRCs. First, there is
DOWN-
SAMPLING
128
UPSAMPLING
64
0.5 1.0 1.5 2.0 FSOUT /FSIN
Figure 8. Number of Filter Taps as a Function of
FSOUT/FSlN
broadband, Gaussian noise which results from polyphase filter
selection quantization. Even though the AD1890/AD1891 have
a large number of polyphase filters (the equivalent of 65,536) to
choose from, the selection is not infinite. Second, there is
narrow-band noise which results from the non-ideal synchroni-
zation of the sample clocks to the system clock MCLK, which
leads to a non-ideal computation of the sample clock ratio,
which leads to a non-ideal polyphase filter selection. This noise
source is narrowband because the digital servo control loop
averages the polyphase filter selection, leading to a strong corre-
lation between selections from output to output. In slow mode,
the selection of polyphase filters is completely unaffected by the
clock synchronization. In fast mode, some narrowband noise
modulation may be observed with very long FFT measure-
ments. This situation is analogous to the behavior of a phase
locked loop when presented with a noisy or jittered input.
Third, there are distortion components that are due to the
non-infinite stopband rejection of the low-pass filter response.
Non-infinite stopband rejection means that some amount of
out-of-band spectral energy will alias into the baseband. The
AD1890/AD1891 performance specifications include the effects
of these phenomena.
Note that Figures 15 through 17 are shown with full-scale input
signals. The distortion and noise components will scale with the
input signal amplitude. In other words, if the input signal is at-
tenuated by –20 dB, the distortion and noise components will
also be attenuated by –20 dB. This dependency holds until the
effects of the 20-bit input quantization are reached.
–12–
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