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PDF AD1881 Data sheet ( Hoja de datos )
| Número de pieza | AD1881 | |
| Descripción | AC97 SoundMAX Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD1881 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
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AC’97 SoundMAX® Codec
AD1885
AC’97 2.1 FEATURES
ENHANCED FEATURES
Variable Sample Rate Audio
Multiple Codec Configuration Options
External Audio Power-Down Control
Full Duplex Variable Sample Rates from 7040 Hz to
48 kHz with 1 Hz Resolution
Jack Sense Pins Provide Automatic Output Switching
AC’97 FEATURES
AC’97 2.1-Compliant
Greater than 90 dB Dynamic Range
Stereo Headphone Amplifier
Multibit ⌺⌬ Converter Architecture for Improved S/N
Ratio Greater than 90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-Level Stereo Inputs for:
Software-Enabled VREFOUT Output for Microphones and
External Power Amp
Split Power Supplies (3.3 V Digital/5 V Analog)
Mobile Low-Power Mixer Mode
Extended 6-Bit Master Volume Control
Extended 6-Bit Headphone Volume Control
Digital Audio Mixer Mode
PHAT™ Stereo 3D Stereo Enhancement
LINE-IN, CD, VIDEO, and AUX
Two Analog Line-Level Mono Inputs for Speakerphone
and PC BEEP
Mono MIC Input w/Built-In 20 dB Preamp, Switchable
from Two External Sources
High Quality CD Input with Ground Sense
Stereo Line-Level Outputs
Mono Output for Speakerphone or Internal Speaker
Power Management Support
48-Terminal LQFP Package
FUNCTIONAL BLOCK DIAGRAM
ID0 ID1
JS0/EAPD JS1
MIC1
MIC2
LINE
AUX
CD
VIDEO
PHONE_IN
MONO_OUT
HP_OUT_L
LINE_OUT_L
AD1885
0dB/
20dB
MMV
HV
MV
⌺
CHIP SELECT
JACK SENSES
AND EAPD CTRL
VREF
PGA
16-BIT
⌺⌬ A/D
CONVERTER
PGA
16-BIT
⌺⌬ A/D
CONVERTER
⌺
POP
G
A
M
⌺
PHAT
STEREO
⌺
G GG G G
⌺ A AA A A
M MM M M
⌺⌺ ⌺ ⌺⌺
SAMPLE
RATE
GENERATORS
NC G
A
M
16-BIT
⌺⌬ D/A
CONVERTER
⌺
VREFOUT
RESET
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
LINE_OUT_R
HP_OUT_R
PC_BEEP
MV
HV
⌺
PHAT
STEREO
⌺
POP
A
M
⌺⌺⌺ ⌺⌺
G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME
HV = HEADPHONE VOLUME
G
A
NC M
16-BIT
⌺⌬ D/A
CONVERTER
⌺
OSCILLATOR
SoundPort is a registered trademark and PHAT is a trademark of Analog Devices, Inc.
XTL_OUT XTL_IN
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
Symbol
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
Min
162.8
162.8
32.56
32.56
5
5
2
2
2
2
2
2
2
2
0
15
NOTES
*Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
Typ
1.0
1.3
19.5
12.288
81.4
42
38
48.0
20.8
2.5
4
4
4
4
4
4
4
4
AD1885
Max
750
48.84
48.84
10
10
10
10
10
10
10
10
10
25
15
50
15
Unit
µs
ns
µs
µs
ns
MHz
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
REV. 0
–5–
5 Page 
AD1885
Indexed Control Registers
Reg
Num Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
00h Reset
X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0410h
02h Master Volume
MM X LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X X RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
04h Headphones Volume HPM X LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 X X RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h
06h Master Volume Mono MMM X X X X X X X X X X MMV MMV MMV MMV MMV 8000h
4 32 10
08h Reserved
X XX X X X X X XXX X X X X X X
0Ah PC Beep Volume
PCM X X X X X X X X X X PCV3 PCV2 PCV1 PCV0 X 8000h
0Ch Phone In Volume
PHM X X
X XX X
X XXX
PHV4 PHV3 PHV2 PHV1 PHV0 8008h
0Eh MIC Volume
MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 8008h
10h Line In Volume
LM
XX
LLV4 LLV3 LLV2 LLV1 LLV0 X X X
RLV4 RLV3 RLV2 RLV1 RLV0 8808h
12h CD Volume
CVM X X
LCV4 LCV3 LCV2 LCV1 LCV0 X X X
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
14h Video Volume
VM X X LVV4 LVV3 LVV2 LVV1 LVV0 X X X RVV4 RVV3 RVV2 RVV1 RVV0 8808h
16h Aux Volume
AM X X LAV4 LAV3 LAV2 LAV1 LAV0 X X X RAV4 RAV3 RAV2 RAV1 RAV0 8808h
18h PCM Out Volume
OM
XX
LOV4 LOV3 LOV2 LOV1 LOV0 X X X
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
1Ah Record Select
X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0000h
1Ch Record Gain
IM X X X LIM3 LIM2 LIM1 LIM0 X X X X RIM3 RIM2 RIM1 RIM0 8000h
1Eh Reserved
X XX X X X X X XXX X X X X X X
20h General Purpose
POP
X 3D X
XX
MIX MS LPBK X X
X
XX
XX
0000h
22h 3D Control
X X X X X X X X X X X X DP3 DP2 DP1 DP0 0000h
26h Power-Down Cntrl/Stat X
X PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh
28h Extended Audio ID
ID1
ID0 X
X XX X
X XXX
X
X X X VRA 0001h
2Ah Extended Audio Stat/Ctrl X
X X X X X X X X X X X X X X VRA 0000h
2Ch/ PCM DAC Rate (SR1) SR15
(7Ah)*
SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
32h/ PCM ADC Rate (SR0) SR15
(78h)*
SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
34h Reserved
X XX X X X X X XXX X X X X X X
.. ..
.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
72h Jack Sense/Audio
Interrupt/Status
JS1_OUT JS0_ JS1 JS0 JS1_ JS0 JS1 JS0 JS1 JS0_ JS1 JS0 AUD JS1 JS0 JS
0000h
FUNCT OUT PUDIS PUDIS OE OE DIS DIS CLR CLR MODE MODE INT
INT
74h Serial Configuration
SLOT
16
REG REG REG X
M2 M1 M0
X
DHWR X
X X X X X X X 7000h
76h Miscellaneous Control DAC
Bits Z
LPMI X
X
DAM DMS DLSR X
ALSR MOD SRX1 SRX8 X
EN 0D7 D7
X DRSR X ARSR 0404h
7Ch Vendor ID1
F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4144h
7Eh Vendor ID2
T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5360h
NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*Indicates Aliased register for AD1819B backward compatibility.
REV. 0
–11–
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet AD1881.PDF ] | |
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