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PDF AD1871 Data sheet ( Hoja de datos )
| Número de pieza | AD1871 | |
| Descripción | Stereo Audio/ 24-Bit/ 96 kHz/ Multibit ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
5.0 V Stereo Audio ADC
with 3.3 V Tolerant Digital Interface
Supports 96 kHz Sample Rates
Supports 16-/20-/24-Bit Word Lengths
Multibit Sigma-Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
105 dB (Typ) Dynamic Range
Supports 256/512 and 768 ؋ fS Master Clocks
Flexible Serial Data Port
Allows Right-Justified, Left-Justified, I2S Compatible
and DSP Serial Port Modes
Cascadable (up to Four Devices) from a Single DSP
SPORT
Device Control via SPI Compatible Serial Port or
Optional Control Pins
On-Chip Reference
28-Lead SSOP Package
APPLICATIONS
Professional Audio
Mixing Consoles
Musical Instruments
Digital Audio Recorders, Including
CD-R, MD, DVD-R, DAT, HDD
Home Theater Systems
Automotive Audio Systems
Multimedia
Stereo Audio, 24-Bit,
96 kHz, Multibit ⌺-⌬ ADC
AD1871
PRODUCT OVERVIEW
The AD1871 is a stereo audio ADC intended for digital audio
applications requiring high performance analog-to-digital
conversion. It features two 24-bit conversion channels each
with programmable gain amplifier (PGA), multibit sigma-delta
modulator, and decimation filters. Each channel provides 105 db
of dynamic range, making the AD1871 suitable for applications
such as digital audio recorders and mixing consoles.
Each of the AD1871’s input channels (left and right) can be
configured as either differential or single-ended (two inputs
muxed with internal single-ended-to-differential conversion).
The input PGA features a gain range of 0 dB to 12 dB in steps
of 3 dB. The Σ-∆ modulator features a proprietary multibit
architecture that realizes optimum performance over an audio
bandwidth with standard audio sampling rates of 32 kHz up to
96 kHz. The decimation filter response features very low pass-
band ripple and excellent stop-band attenuation.
The AD1871’s audio data interface supports all common interface
formats such as I2S, left-justified, right-justified as well as other
modes that allow for convenient connection to general-purpose
digital signal processors (DSPs). The AD1871 also features an
SPI compatible serial control port that allows for convenient
control of device parameters and functionality such as sample
word-width, PGA settings, interface modes, and so on.
The AD1871 operates from a single 5 V power supply—with
an optional digital interfacing capability of 3.3 V. It is housed in
a 28-lead SSOP package and is characterized for operation
over the temperature range –40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
CAPLN CAPLP
AVDD
DVDD
ODVDD
CASC
VINLP
VINLN
ANALOG
INPUT
BUFFER
VREF
MULTIBIT
⌺-⌬
MODULATOR
DECIMATOR
AD1871
FILTER
ENGINE
DATA
PORT
CLOCK
DIVIDER
LRCLK
BCLK
DOUT
DIN
RESET
MCLK
VINRP
VINRN
ANALOG
INPUT
BUFFER
MULTIBIT
⌺-⌬
MODULATOR
DECIMATOR
SPI
PORT
CLATCH/(M/S)
CCLK/(256/512)
CIN/(DF1)
COUT/(DF0)
XCTRL
CAPRN CAPRP
AGND
DGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
DATA INTERFACE TIMING (STANDALONE MODE–MASTER)
Mnemonic
tBDLY
tBLDLY
tBDDLY
Description
BCLK Delay
LRCLK Delay to Low
DOUT Delay
Min Typ Max
20
10
10
Unit
ns
ns
ns
Comment
From MCLK Rising
From BCLK Falling
From BCLK Falling
AD1871
MCLK
tBDLY
BCLK
tBLDLY
LRCLK
DOUT
LEFT-JUSTIFIED
MODE
tBDDLY
MSB
MSB–1
DOUT
I2S-JUSTIFIED
MODE
MSB
DOUT
RIGHT-JUSTIFIED
MODE
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Master Data Interface Timing
LSB
REV. 0
–5–
5 Page 
AD1871
Pin Function Redefinition in External Control Mode
Pin Input/
No. Output Mnemonic
Description
2I
3I
4I
5I
256/512
DF0
DF1
M/S
Clock Rate Select. This pin is used to select between an MCLK of 256 ϫ fS (pin low) or
512 ϫ fS (pin high).
Data Format Select 0. This pin is used as the low bit (DF0) of the data format selection
(see section on External Control).
Data Format Select 1. This pin is used as the high bit (DF1) of the data format selection
(see section on External Control).
Master/Slave Select. This pin is used to select between the Master (pin low) or Slave (pin
high) Modes.
Pin Function Redefinition in Modulator Mode
Pin Input/
No. Output Mnemonic
Description
3O
25 O
26 O
27 O
28 O
MODCLK
D3
D2
D1
D0
This pin provides a clock output that allows the user to decode the left and right channel
modulator outputs. It is similar to a left/right clock but runs (nominally) at 5.6448 MHz
and gates a 4-bit modulator output word in each phase (see section on Modulator Mode).
Bit 3 of the Modulator Output Word
Bit 2 of the Modulator Output Word
Bit 1 of the Modulator Output Word
Bit 0 of the Modulator Output Word
REV. 0
–11–
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD1871.PDF ] | |
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