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AD1859 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1859
Beschreibung Stereo/ Single-Supply 18-Bit Integrated DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD1859 Datasheet, Funktion
a
Stereo, Single-Supply
18-Bit Integrated ⌺⌬ DAC
AD1859
FEATURES
Complete, Low Cost Stereo DAC System in a Single Die
Package
Variable Rate Oversampling Interpolation Filter
Multibit ⌺⌬ Modulator with Triangular PDF Dither
Discrete and Continuous Time Analog Reconstruction
Filters
Extremely Low Out-of-Band Energy
64 Step (1 dB/Step) Analog Attenuator with Mute
Buffered Outputs with 2 kOutput Load Drive
Rejects Sample Clock Jitter
94 dB Dynamic Range, –88 dB THD+N Performance
Option for Analog De-emphasis Processing with
External Passive Components
؎0.1؇ Maximum Phase Linearity Deviation
Continuously Variable Sample Rate Support
Digital Phase Locked Loop Based Asynchronous Master
Clock
On-Chip Master Clock Oscillator, Only External Crystal
Is Required
Power-Down Mode
Flexible Serial Data Port (I2S-Justified, Left-Justified,
Right-Justified and DSP Serial Port Modes)
SPI* Compatible Serial Control Port
Single +5 V Supply
28-Pin SOIC and SSOP Packages
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Digital Video Disc, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players
Digital Audio Workstations, Computer Multimedia
Products
PRODUCT OVERVIEW
The AD1859 is a complete 16-/18-bit single-chip stereo digital
audio playback subsystem. It comprises a variable rate digital
interpolation filter, a revolutionary multibit sigma-delta (∑∆)
modulator with dither, a jitter-tolerant DAC, switched capacitor
and continuous time analog filters, and analog output drive cir-
cuitry. Other features include an on-chip stereo attenuator and
mute, programmed through an SPI-compatible serial control
port.
The key differentiating feature of the AD1859 is its asynchro-
nous master clock capability. Previous ∑∆ audio DACs re-
quired a high frequency master clock at 256 or 384 times the
intended audio sample rate. The generation and management
of this high frequency synchronous clock is burdensome to the
board level designer. The analog performance of conventional
single bit ∑∆ DACs is also dependent on the spectral purity of
the sample and master clocks. The AD1859 has a digital Phase
Locked Loop (PLL) which allows the master clock to be asyn-
chronous, and which also strongly rejects jitter on the sample
clock (left/right clock). The digital PLL allows the AD1859 to
be clocked with a single frequency (27 MHz for example) while
the sample frequency (as determined from the left/right clock)
can vary over a wide range. The digital PLL will lock to the
new sample rate in approximately 100 ms. Jitter components
15 Hz above and below the sample frequency are rejected by
6 dB per octave. This level of jitter rejection is unprecedented
in audio DACs.
The AD1859 supports continuously variable sample rates with
essentially linear phase response, and with an option for external
analog de-emphasis processing. The clock circuit includes an
on-chip oscillator, so that the user need only provide an external
crystal. The oscillator may be overdriven, if desired, with an ex-
ternal clock source.
(continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
SUPPLY
2
CONTROL
DATA
INPUT
3
REFERENCE
FILTER AND
GROUND
2
ASYNCHRONOUS
CLOCK/CRYSTAL
16- OR 18-BIT 6
DIGITAL DATA
INPUT
AD1859
SERIAL
DATA
INTERFACE
VARIABLE RATE
INTERPOLATION
VARIABLE RATE
INTERPOLATION
POWER
DOWN/RESET
SERIAL
CONTROL
INTERFACE
VOLTAGE
REFERENCE
MULTIBIT
∑∆ MODULATOR
DAC
ANALOG
FILTER
MULTIBIT
∑∆ MODULATOR
DAC
ANALOG
FILTER
MUTE
DE-EMPHASIS
DPLL/CLOCK
MANAGER
ATTEN/
MUTE
ATTEN/
MUTE
OUTPUT
BUFFER
OUTPUT
BUFFER
2
ANALOG
SUPPLY
DE-EMPHASIS
SWITCH LEFT
COMMON MODE
ANALOG
OUTPUTS
DE-EMPHASIS
SWITCH RIGHT
*SPI is a registered trademark of Motorola, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD1859 Datasheet, Funktion
AD1859
PIN DESCRIPTIONS
Analog Signals
Control and Clock Signals
Pin Name Number I/O Description
Pin Name Number I/O Description
FILT
28
FGND
27
CMOUT 1
OUTL
OUTR
EMPL
4
25
3
EMPR
26
O Voltage reference filter capacitor
connection. Bypass and decouple
the voltage reference with paral-
lel 10 µF and 0.1 µF capacitors
to the FGND pin.
I Voltage reference filter ground.
Use exclusively for bypassing and
decoupling of the FILT pin
(voltage reference).
O Voltage reference common-mode
output. Should be decoupled
with 10 µF capacitor to the AGND
pin or plane. This output is available
externally for dc-coupling and level-
shifting. CMOUT should not have
any signal dependent load, or where
it will sink or source current.
O Left channel line level analog output.
O Right channel line level analog output.
O De-emphasis switch connection
for the left channel. Can be left
unconnected if de-emphasis is not
required in the target application.
O De-emphasis switch connection
for the right channel. Can be left
unconnected if de-emphasis is not
required in the target application.
PD/RST
DEEMP
MUTE
XTALI/
MCLK
XTALO
11
2
7
16
15
I Power down/reset. The AD1859 is
placed in a low power consumption
“sleep” mode when this pin is held
LO. The AD1859 is reset on the
rising edge of this signal. The serial
control port registers are reset to
their default values. Connect HI
for normal operation.
I De-emphasis. An external analog de-
emphasis circuit network is enabled
when this input signal is HI. This
circuit is typically used to impose a
50/15 µs (or perhaps the CCITT
J.17) response characteristic on the
output audio spectrum.
I Mute. Assert HI to mute both
stereo analog outputs of the AD1859.
Deassert LO for normal operation.
I Crystal input or master clock input.
Connect to one side of a quartz
crystal to this input, or connect to
an external clock source to over-
drive the on-chip oscillator.
O Crystal output. Connect to other
side of a quartz crystal. Do not con-
nect if using the XTALI/MCLK
pin with an external clock source.
Power Supply Connections and Miscellaneous
Pin Name Number I/O Description
AVDD
AGND
DVDD
DGND
NC
23 I
6I
17 I
18 I
5, 22, 24
Analog Power Supply. Connect
to analog +5 V supply.
Analog Ground.
Digital Power Supply. Connect
to digital +5 V supply.
Digital Ground.
No Connect. Reserved. Do not
connect.
–6– REV. A

6 Page









AD1859 pdf, datenblatt
AD1859
Figure 15 shows the suggested interface to the Zoran ZR38000
DSP chip, which can act as an MPEG audio or AC-3 audio
decoder. The ZR38000 supports 16 bits of data using a left-
justified output format.
ZORAN
ZR38000
SCKB
WSB
SDB
SCKIN
14 BCLK
13 LRCLK
12 SDATA AD1859
LO 9 IDPM0
256 x FS
HI 10 IDPM1
LO 8 18/16
Figure 15. Interface to ZR38000
Figure 16 shows the suggested interface to the C-Cube
Microsystems CL480 MPEG system decoder IC. The CL480
supports 16 bits of data using a right-justified output format.
C-CUBE
CL480
DA-BCK
DA-LRCK
DA-DATA
DA-XCK
256 x FS
OR
384 x FS
LO
LO
LO
14 BCLK
13 LRCLK
12 SDATA
9 IDPM0
10 IDPM1
8 18/16
AD1859
Figure 16. Interface to CL480
Layout and Decoupling Considerations
The recommended decoupling, bypass circuits for the AD1859
are shown in Figure 17. Figure 17 illustrates a connection dia-
gram for systems which do not require de-emphasis support.
The recommended circuit connection for system including de-
emphasis is shown in Figure 18.
DSP OR
AUDIO
DECODER
+5V ANALOG
1µF
0.1µF
µCONTROLLER
20-64pF
20-64pF
27MHz
23
AVDD
12 SDATA
14 BLCK
13 LRCLK
9 IDPM0
10 IDPM1
8 18/16
DVDD
17
6
20 19
21
16 15
AGND CDATA CCLK CLATCH XTALI/MCLK XTALO
FILT 28
FGND 27
CMOUT 1
ADA1D8158959
NC 5
NC 24
OUTL 4
EMPL 3
DGND
18
NC
22
PD/RST MUTE DEEMP
11 7
2
OUTR 25
EMPR 26
30
(CHIP RESISTOR
PREFERRED)
0.01µF
1µF
µCONTROLLER
+5V DIGITAL
10µF
1k
1k
0.1µF
BIAS VOLTAGE
10µF 0.1µF FOR EXTERNAL USE
10µF
2.2nF
10µF
2.2nF
LEFT LINE
OUTPUT
RIGHT LINE
OUTPUT
Figure 17. Recommended Circuit Connection (Without De-emphasis)
DSP OR
AUDIO
DECODER
+5V ANALOG
1µF
0.1µF
µCONTROLLER
20-64pF
20-64pF
27MHz
23
AVDD
12 SDATA
14 BLCK
13 LRCLK
9 IDPM0
10 IDPM1
8 18/16
DVDD
17
6 20
AGND CDATA
DGND
18
19 21
16 15
CCLK CLATCH XTALI/MCLK XTALO
FILT 28
FGND 27
CMOUT 1
AD1859
NC 5
NC 24
OUTL 4
EMPL 3
OUTR 25
NC PD/RST MUTE DEEMP EMPR 26
22
11 7
2
30
(CHIP RESISTOR
PREFERRED)
0.01µF
1µF
µCONTROLLER
10µF
0.1µF
10µF 0.1µF
1µF
1k2.2nF
1k
2.2nF
470
33nF
NPO
470
33nF
NPO
10M
1µF
10M
OPTIONAL DE-EMPHASIS
CIRCUIT SHOWN
+5V DIGITAL
BIAS VOLTAGE
FOR EXTERNAL USE
LEFT LINE
OUTPUT
RIGHT LINE
OUTPUT
Figure 18. Recommended Circuit Connection (With De-emphasis)
–12–
REV. A

12 Page





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