AD1855 Datasheet PDF - Analog Devices
| Part Number | AD1855 | |
| Description | Stereo/ 96 kHz/ Multibit DAC | |
| Manufacturers | Analog Devices | |
| Logo |  |
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a
Stereo, 96 kHz, Multibit ⌺⌬ DAC
AD1855*
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulator with “Perfect Differen-
tial Linearity Restoration” for Reduced Idle Tones
and Noise Floor
Data Directed Scrambling DAC—Least Sensitive to
Jitter
Differential Output for Optimum Performance
113 dB Signal-to-Noise and Dynamic Range at 48 kHz
Sample Rate
110 dB Signal-to-Noise and Dynamic Range at 96 kHz
Sample Rate
–97 dB THD+N
On-Chip Volume Control with 1024 Steps
Hardware and Software Controllable Clickless Mute
Zero Input Flag Outputs for Left and Right Channels
Digital De-Emphasis Processing
Supports 128, 256, 384, and 512 ؋ FS Master Mode
Clock
Switchable Clock Doubler
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Set-Top Boxes, Home Theater Systems, Auto-
motive Audio Systems, Computer Multimedia Prod-
ucts, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1855 is a high performance, single-chip stereo, audio
DAC delivering 113 dB Dynamic Range and SNR (A-weighted—
not muted) at 48 kHz sample rate. It is comprised of a multibit
sigma-delta modulator with dither, continuous time analog
filters and analog output drive circuitry. Other features include
an on-chip stereo attenuator and mute, programmed through an
SPI-compatible serial control port. The AD1855 is fully com-
patible with current DVD formats, including 96 kHz sample
frequency and 24 bits. It is also backwards compatible by sup-
porting 50 µs/15 µs digital de-emphasis intended for “redbook”
44.1 kHz sample frequency playback from compact discs.
The AD1855 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The AD1855 can be configured in left-justified, I2S, right-
justified, or DSP serial port compatible modes. The AD1855
accepts 16-/18-/20-/24-bit serial audio data in MSB first, twos-
complement format. A power-down mode is offered to mini-
mize power consumption when the device is inactive. The
AD1855 operates from a single +5 V power supply. It is fabri-
cated on a single monolithic integrated circuit and housed in a
28-lead SSOP package for operation over the temperature range
0°C to +70°C.
FUNCTIONAL BLOCK DIAGRAM
CONTROL DATA
VOLUME INPUT
MUTE
3
DIGITAL
SUPPLY
CLOCK
IN
96/48FS
CLOCK
2
AD1855
SERIAL CONTROL VOLTAGE
INTERFACE
REFERENCE
CLOCK
CIRCUIT
384/ 256
X2MCLK
16-/18-/20-/24-BIT 3
DIGITAL
DATA INPUT
SERIAL 2
MODE
SERIAL
DATA
INTERFACE
ATTEN/
MUTE
ATTEN/
MUTE
PD /RST
8؋
INTERPOLATOR
8؋
INTERPOLATOR
MUTE
MULTIBIT SIGMA-
DELTA MODULATOR
MULTIBIT SIGMA-
DELTA MODULATOR
DAC
DAC
DE-EMPHASIS
2
ANALOG
SUPPLY
OUTPUT
BUFFER
OUTPUT
BUFFER
2
ZERO
FLAG
ANALOG
OUTPUTS
*Patents Pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
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Pin Input/Output
1I
2I
3I
4I
5I
6I
7I
8O
9I
10
11, 15
12
13
14
I
I
O
O
O
16 O
17 O
18 I
19 O
20 I
21 I
22 O
23 I
24 I
25 I
26 I
27 I
28 I
AD1855
Pin Name
DGND
MCLK
CLATCH
CCLK
CDATA
384/256
X2MCLK
ZEROR
DEEMP
96/48
AGND
OUTR+
OUTR–
FILTR
OUTL–
OUTL+
AVDD
FILTB
IDPM1
IDPM0
ZEROL
MUTE
PD/RST
L/RCLK
BCLK
SDATA
DVDD
PIN FUNCTION DESCRIPTIONS
Description
Digital Ground.
Master Clock Input. Connect to an external clock source at either 128, 256,
384 or 512 FS , based on sample rate and clock doubler mode.
Latch input for control data. This input is rising-edge sensitive.
Control clock input for control data. Control input data must be valid on the
rising edge of CCLK. CCLK may be continuous or gated.
Serial control input, MSB first, containing 16 bits of unsigned data per
channel. Used for specifying channel specific attenuation and mute.
Selects the master clock mode as either 384 times the intended sample fre-
quency (HI) or 256 times the intended sample frequency (LO). The state of
this input should be hardwired to logic HI or logic LO, or may be changed
while the AD1855 is in power-down/reset. It must not be changed while the
AD1855 is operational.
Selects internal clock doubler (LO) or internal clock = MCLK (HI).
Right Channel Zero Flag Output. This pin goes HI when Right Channel has
no signal input for more than 1024 LR Clock Cycles.
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.
This is used to impose a 50 µs/15 µs response characteristic on the output
audio spectrum at an assumed 44.1 kHz sample rate.
Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
Analog Ground.
Right Channel Positive line level analog output.
Right Channel Negative line level analog output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 µF and 0.1 µF capacitors to the AGND.
Left Channel Negative line level analog output.
Left Channel Positive line level analog output.
Analog Power Supply. Connect to analog +5 V supply.
Filter Capacitor connection, connect 10 µF capacitor to AGND.
Input serial data port mode control one. With IDPM0, defines one of four
serial modes.
Input serial data port mode control zero. With IDPM1, defines one of four
serial modes.
Left Channel Zero Flag output. This pin goes HI when Left Channel has no
signal input for more than 1024 LR Clock Cycles.
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-
mal operation.
Power-Down/Reset. The AD1855 is placed in a low power consumption
mode when this pin is held LO. The AD1855 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values.
Connect HI for normal operation. A reset should always be performed at
power-on.
Left/Right clock input for input data. Must run continuously.
Bit clock input for input data. Need not run continuously; may be gated or
used in a burst fashion.
Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of
twos complement data per channel.
Digital Power Supply Connect to digital +5 V supply.
REV. B
–5–
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| Information | Total 15 Pages | |
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| Download | [ AD1855.PDF Datasheet ] | |
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