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AD1845 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1845
Beschreibung Parallel-Port 16-Bit SoundPort Stereo Codec
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD1845 Datasheet, Funktion
a
Parallel-Port 16-Bit
SoundPort® Stereo Codec
AD1845
FEATURES
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Microsoft® and Windows® Sound System Compatible
MPC Level-2+ Compliant Mixing
16 mA Bus Drive Capability
Supports Two DMA Channels for Full Duplex Operation
On-Chip Capture and Playback FIFOs
Advanced Power-Down Modes
Programmable Gain and Attenuation
Sample Rates from 4.0 kHz to 50 kHz Derived from a
Single Clock or Crystal Input
68-Lead PLCC, 100-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Pin Compatible with AD1848, AD1846, CS4248, CS4231
PRODUCT OVERVIEW
The Parallel Port AD1845 SoundPort Stereo Codec integrates
key audio data conversion and control functions into a single
integrated circuit. The AD1845 provides a complete, single chip
computer audio solution for business audio and multimedia
applications. The codec includes stereo audio converters, com-
plete on-chip filtering, MPC Level-2 compliant analog mixing,
programmable gain, attenuation and mute, a variable sample
frequency generator, FIFOs, and supports advanced power-
down modes. It provides a direct, byte-wide interface to both
ISA (“AT”) and EISA computer buses for simplified implemen-
tation on a computer motherboard or add-in card.
The AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
Two input control lines support mixed direct and indirect ad-
dressing of thirty-seven internal control registers over this asyn-
chronous interface. The AD1845 includes dual DMA count
registers for full duplex operation enabling the AD1845 to cap-
ture data on one DMA channel and play back data on a separate
channel. The FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. The
FIFOs buffer data transfers and allow for relaxed timing in
acknowledging requests for capture and playback data.
(Continued on Page 9)
FUNCTIONAL BLOCK DIAGRAM
ANALOG
ANALOG SUPPLY
DIGITAL SUPPLY
CLOCK SOURCE POWER DOWN
RESET
DIGITAL
L_MIC
R_MIC
L_LINE
R_LINE
L_AUX1
R_AUX1
L_OUT
M_OUT
R_OUT
M_IN
L_AUX2
R_AUX2
0 dB/
20 dB
VARIABLE SAMPLE
FREQUENCY GENERATOR
L
M
U
XR
GAIN
GAIN
⌺⌬ A/D
CONVERTER
⌺⌬ A/D
CONVERTER
AD1845
-LAW
A-LAW
LINEAR
FIFO
MUTE
GAM
GAM
GAM
GAM = GAIN
ATTENTUATE
MUTE
DIGITAL MIX
ATTENUATE
L ATTENUATE
MUTE
⌺⌬ D/A
CONVERTER
R
ATTENUATE
MUTE
⌺⌬ D/A
CONVERTER
-LAW
A-LAW
LINEAR
GAM
GAM
FIFO
P
A
R
A
L
L
E
L
P
O
R
T
PLAYBACK REQ
PLAYBACK ACK
CAPTURE REQ
CAPTURE ACK
ADR1:0
DATA7:0
CS
RD
WR
BUS DRIVER
CONTROL
HOST DMA
INTERRUPT
EXTERNAL
CONTROL
REFERENCE
CONTROL
REGISTERS
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
VREF_F VREF
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997






AD1845 Datasheet, Funktion
AD1845
PIN DESIGNATIONS
68-Lead PLCC
ADR0 10
CDAK 11
CDRQ 12
PDAK 13
PDRQ 14
VDD 15
GNDD 16
XTAL1I 17
XTAL1O 18
VDD 19
GNDD 20
XTAL2I 21
XTAL2O 22
PWRDWN 23
RESET 24
GNDD 25
R_FILT 26
ADR0 1
NC 2
NC 3
NC 4
NC 5
CDAK 6
CDRQ 7
PDAK 8
PDRQ 9
VDD 10
GNDD 11
100-Lead TQFP XTAL1I 12
XTAL1O 13
VDD 14
GNDD 15
XTAL2I 16
XTAL2O 17
PWRDWN 18
RESET 19
GNDD 20
NC 21
NC 22
NC 23
NC 24
R_FILT 25
AD1845
TOP VIEW
(Not to Scale)
AD1845
TOP VIEW
(Not to Scale)
–6–
60 RD
59 CS
58 XCTL1
57 INT
56 XCTL0
55 NC
54 VDD
53 GNDD
52 NC
51 NC
50 NC
49 NC
48 NC
47 M_OUT
46 M_IN
45 VDD
44 GNDD
NC = NO CONNECT
75 RD
74 CS
73 XCTL1
72 INT
71 XCTL0
70 NC
69 NC
68 VDD
67 GNDD
66 NC
65 NC
64 NC
63 NC
62 NC
61 NC
60 NC
59 NC
58 NC
57 M_OUT
56 M_IN
55 VDD
54 GNDD
53 NC
52 NC
51 NC
NC = NO CONNECT
REV. C

6 Page









AD1845 pdf, datenblatt
AD1845
A write to or a read from the Indexed Data Register will access the Indirect Register which is indexed by the value most recently
written to the Index Address Register. The Status Register and the PIO Data Register are always accessible directly, without
indexing. The 32 Indirect Register indexes are shown in Figure 5:
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Register Name
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #1 Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left Output Control
Right Output Control
Clock and Data Format
Interface Configuration
Pin Control
Test and Initialization
Miscellaneous Information
Digital Mix/Attenuation
Upper Base Count
Lower Base Count
Alternate Feature Enable/Left MIC Input Control
MIC Mix Enable/Right MIC Input Control
Left Line Gain, Attenuate, Mute, Mix
Right Line Gain, Attenuate, Mute, Mix
Lower Timer
Upper Timer
Upper Frequency Select
Lower Frequency Select
Capture Playback Timer
Revision ID
Mono Control
Power-Down Control
Capture Data Format Control
Crystal Clock Select/Total Power-Down
Capture Upper Base Count
Capture Lower Base Count
Reset/Default State
000x
000x
0000
0000
1xx0 1000
1xx0 1000
1xx0 1000
1xx0 1000
1x00
1x00
0000
0000
0000
00xx
0000
1000
00xx
0000
xx00
0000
10x0
0000
1010
00x0
0000
0000
0000
0000
0001
0001
0001
000x
1xx0 1000
1xx0 1000
0000
0000
0000
0000
0001
0100
1111
0000
x000
100x
0000
x000
00xx
000x
0011
0xxx
0000
000x
xxxx
xxx0
0000
0000
0000
0000
“x” indicates reserved bit, always write “0s” to these bits.
Figure 5. Indirect Register Map and Reset/Default States
A detailed map of all direct and indirect register contents is summarized for reference as follows:
–12–
REV. C

12 Page





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