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AD1837 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1837
Beschreibung 2 ADC/ 8 DAC/ 96 kHz/ 24-Bit Codec
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD1837 Datasheet, Funktion
2 ADC, 8 DAC,
96 kHz, 24-Bit -Codec
AD1837
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant
Digital Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on One DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit -Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Single-Ended Outputs
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –92 dB THD + N, 108 dB SNR and
Dynamic Range
On-Chip Volume Controls per Channel with
1024-Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
Supports 256 ؋ fS, 512 ؋ fS, and 768 ؋ fS Master Mode
Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1837 is a high performance single-chip codec featuring
four stereo DACs and one stereo ADC. Each DAC comprises a
high performance digital interpolation filter, a multibit -
modulator featuring Analog Devices’ patented technology, and
a continuous-time voltage out analog section. Each DAC has
independent volume control and clickless mute functions. The
ADC comprises two 24-bit conversion channels with multibit
-modulators and decimation filters.
The AD1837 also contains an on-chip reference with a nominal
value of 2.25 V.
The AD1837 contains a flexible serial interface that allows for
glueless connection to a variety of DSP chips, AES/EBU receiv-
ers, and sample rate converters. The AD1837 can be configured
in left-justified, right-justified, I2S, or DSP compatible serial
modes. Control of the AD1837 is achieved by means of an SPI
compatible serial port. While the AD1837 can be operated from
a single 5 V supply, it also features a separate supply pin for its
digital interface that allows the device to be interfaced to other
devices using 3.3 V power supplies.
The AD1837 is available in a 52-lead MQFP package and is
specified for the industrial temperature range of –40ºC to +85ºC.
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT MCLK PD/RST M/S AVDD AVDD
REV. B
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ADCLP
ADCLN
ADCRP
ADCRN
-
ADC
-
ADC
AD1837
SERIAL DATA
I/O PORT
DIGITAL
FILTER
DIGITAL
FILTER
CONTROL PORT
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
CLOCK
DIGITAL
FILTER
DIGITAL
FILTER
DIGITAL
FILTER
DIGITAL
FILTER
DGND DGND AGND AGND AGND AGND
-
DAC
-
DAC
-
DAC
-
DAC
VREF
OUTL1
OUTR1
OUTL2
OUTR2
OUTL3
OUTR3
OUTL4
OUTR4
FILTD
FILTR
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD1837 Datasheet, Funktion
AD1837
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
AVDD, DVDD, ODVDD to AGND, DGND . . . . –0.3 V to +6.0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to ODVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40C to +85C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Parameter
Specifications
Guaranteed
Functionality
Guaranteed
Storage
TEMPERATURE RANGE
Min Typ Max
25
–40 +85
–65 +150
Unit
C
C
C
Model
AD1837AS
AD1837AS-REEL
EVAL-AD1837EB
ORDERING GUIDE
Temperature
Range
–40oC to +85oC
–40oC to +85oC
Package
Description
52-Lead MQFP
52-Lead MQFP
Evaluation Board
Package
Option
S-52A
S-52A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1837 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–6– REV. B

6 Page









AD1837 pdf, datenblatt
AD1837
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the DAC
outputs if the jitter spectrum contains large spectral peaks. It is
highly recommended that the master clock be generated by an
independent crystal oscillator. In addition, it is especially important
that the clock signal should not be passed through an FPGA or
other large digital chip before being applied to the AD1837. In
most cases, this will induce clock jitter due to the fact that the
clock signal is sharing common power and ground connections
with other unrelated digital output signals.
RESET and Power-Down
PD/RST will power down the chip and set the control regis-
ters to their default settings. After PD/RST is deasserted, an
initialization routine will run inside the AD1837 to clear all
memories to zero. This initialization lasts for approximately
20 LRCLK intervals. During this time, it is recommended that
no SPI writes occur.
Power Supply and Voltage Reference
The AD1837 is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as close
to the pins as possible, to minimize noise pickup. A bulk alumi-
num electrolytic capacitor of at least 22 mF should also be provided
on the same PC board as the codec. For critical applications,
improved performance will be obtained with separate supplies for
the analog and digital sections. If this is not possible, it is recom-
mended that the analog and digital supplies be isolated by means of
two ferrite beads in series with the bypass capacitor of each supply.
It is important that the analog supply be as clean as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 mF and 100 nF. The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the FILTR pin should be limited to less than 5 mA.
Serial Control Port
The AD1837 has an SPI® compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control
port. The format is similar to the Motorola SPI format except the
input data-word is 16 bits wide. The maximum serial bit clock
frequency is 12.5 MHz and may be completely asynchronous to
the sample rate of the ADCs and DACs. Figure 3 shows the
format of the SPI signal.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to right-justified
(RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ
mode, it is necessary to set Bits 4 and 5 to define the width of
the data-word.
The DAC serial data input mode defaults to I2S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2.
The word width defaults to 24 bits but can be changed by
reprogramming Bits 3 and 4 in DAC Control Register 1.
Packed Modes
The AD1837 has a packed mode that allows a DSP or other
controller to write to all DACs and read all ADCs using one
input data pin and one output data pin. Packed Mode 256
refers to the number of BCLKs in each frame. The LRCLK is
low while data from a left channel DAC or ADC is on the data
pin and high while data from a right channel DAC or ADC is
on the data pin. DAC data is applied on the DSDATA1 pin and
ADC data is available on the ASDATA pin. Figures 7 to 10
show the timing for the packed mode. Packed mode is available
only for 48 kHz (based on MCLK = 12.288 MHz) and when
the ADC is set as a master (M/S = 0).
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external
stereo ADCs to be interfaced to the AD1837 to provide 8-in/8-out
operation. In addition, this mode supports glueless interface to a
single SHARC DSP serial port, allowing a SHARC DSP to
access all eight channels of analog I/O. In this special mode,
many pins are redefined; see Table II for a list of redefined pins.
The auxiliary and the TDM interfaces are independently config-
urable to operate as masters or slaves. When the auxiliary interface
is set as a master, by programming the Aux Mode bit in ADC
Control Register 2, AUXLRCLK and AUXBCLK are generated
by the AD1837. When the auxiliary interface is set as a slave, the
AUXLRCLK and AUXBCLK need to be generated by an external
ADC as shown in Figure 13.
The TDM interface can be set to operate as a master or slave by
connecting the M/S pin to DGND or ODVDD, respectively. In
master mode, the FSTDM and BCLK signals are outputs and
are generated by the AD1837. In slave mode, the FSTDM and
BCLK are inputs and should be generated by the SHARC. Slave
mode operation is available for 48 kHz and 96 kHz operation
(based on a 12.288 MHz or 24.576 MHz MCLK), and master
mode operation is available for 48 kHz only.
–12–
REV. B

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