|
|
PDF AD1836 Data sheet ( Hoja de datos )
| Número de pieza | AD1836 | |
| Descripción | Multichannel 96 kHz Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD1836 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
Multichannel 96 kHz Codec
AD1836
FEATURES
5 V Multichannel Audio System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulators with Data Directed
Scrambling
Data-Directed Scrambling ADCs and DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –92 dB THD + N, 105 dB SNR and Dynamic Range
DACs: –95 dB THD + N, 108 dB SNR and Dynamic Range
On-Chip Volume Control with “Autoramp” Function
Programmable Gain Amplifier for ADC Input
Hardware and Software Controllable Clickless Mute
Digital De-Emphasis Processing
Supports 256 ؋ fS, 512 ؋ fS, or 768 ؋ fS Master Clock
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
52-Lead MQFP (PQFP) Plastic Package
APPLICATIONS
Home Theatre Systems
Automotive Audio Systems
DVD
Set-Top Boxes
Digital Audio Effects Processors
GENERAL DESCRIPTION
The AD1836 is a high-performance, single-chip codec pro-
viding three stereo DACs and two stereo ADCs using ADI’s
patented multibit sigma-delta architecture. An SPI port is
included, allowing a microcontroller to adjust volume and
many other parameters. The AD1836 operates from a 5 V
supply, with provision for a separate output supply to interface
with low-voltage external circuitry. The AD1836 is available
in a 52-lead MQFP (PQFP) package.
FUNCTIONAL BLOCK DIAGRAM
CCLK CDATA CLATCH COUT
MCLK
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
ALRCLK
ABCLK
ASDATA1
ASDATA2
AIN1L
AIN1R
CAPL1
AIN2L1
AIN2L2
CAPL2
CAPR1
AIN2R1
AIN2R2
CAPR2
SERIAL
DATA
I/O
PORT
CONTROL PORT
CLOCK
VOLUME
VOLUME
DIGITAL
FILTER
⌺⌬
DAC
⌺⌬
ADC1L
48/96kHz
⌺⌬
ADC1R
48/96kHz
DIGITAL
FILTER
48/96kHz
DIGITAL
FILTER
48/96kHz
PGA
⌺⌬
ADC2L
48kHz
DIGITAL
FILTER
48kHz
VOLUME
VOLUME
DIGITAL
FILTER
VOLUME
VOLUME
DIGITAL
FILTER
⌺⌬
DAC
⌺⌬
DAC
PGA
⌺⌬
ADC2R
48kHz
DIGITAL
FILTER
48kHz
2
PWRDWN/RESET AVDD
4
AGND
3
DVDD
VREF
2
DGND
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
FILTD
FILTR
SHARC is a registered trademark of Analog Device, Inc.
REV. PrC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
PRELIMINARY TECHNICAL DATA
TIMING (continued)
Parameter
TDM, PACKED AUX, SLAVE MODE
tABH
tABL
tABP
fAB
tALS
tALH
tABDD
tALRDD
ABCLK High
ABCLK Low
ABCLK Period
ABCLK Freq
LRCLK Setup
LRCLK Hold
ASDATA Delay
ASDATA Delay
tAXDS
tAXDH
tDDS
tDDH
tDXDD
tDXDD
AAUXDATA Setup
AAUXDATA Hold
DSDATA Setup
DSDATA Hold
DAUXDATA Delay
DAUXDATA Delay
Min Max Unit
min ns
min ns
min ns
max ns
min ns
min ns
max ns
max ns
min ns
min ns
min ns
min ns
max ns
max ns
AD1836
Comments
To ABCLK Rising
To ABCLK Rising
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
To AUXBCLK Rising
From AUXBCLK Rising
To DBCLK Rising
From DBCLK Rising
From AUXBCLK Falling
From AUXLRCLK Changing
(Left-Justified)
POWER SUPPLIES
Parameter
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current, Power-Down
Digital Current
Digital Current, Power-Down
Dissipation
Operation, Both Supplies
Operation, Analog Supply
Operation, Digital Supply
Power-Down, Both Supplies
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Min Typ Max
4.5 5
5.5
108
47
78
1.5
930
540
390
243
–60
–50
Unit
V
mA
mA
mA
mA
mW
mW
mW
mW
dB
dB
TEMPERATURE RANGE
Parameter
Specifications Guaranteed
Functionality Guaranteed
Storage
Specifications subject to change without notice.
Min Typ Max
25
–40
–65
+85
+150
Unit
°C
°C
°C
REV. PrC
–5–
5 Page 
PRELIMINARY TECHNICAL DATA
LRCLK
BCLK
DATA
32 BCLKs
SLOT 1
LEFT 0
128 BCLKs
SLOT 2
LEFT 1
SLOT 3
RIGHT 0
SLOT 4
RIGHT 1
MSB MSB–1 MSB–2
Figure 4. ADC Packed Mode 128
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
SLOT 4
SLOT 5
RIGHT 0
SLOT 6
RIGHT 1
SLOT 7
SLOT 8
MSB MSB–1 MSB–2
Figure 5. ADC Packed Mode 256
LRCLK
BCLK
DATA
20 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
128 BCLKs
SLOT 3
LEFT 2
SLOT 4 SLOT 5 SLOT 6
RIGHT 0 RIGHT 1 RIGHT 2
MSB MSB–1 MSB–2
LRCLK
BCLK
DATA
Figure 6. DAC Packed Mode 128
LRCLK
BCLK
DATA
32 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
256 BCLKs
SLOT 3
LEFT 2
SLOT 4 SLOT 5 SLOT 6
RIGHT 0 RIGHT 1 RIGHT 2
MSB
MSB–1
MSB–2
LRCLK
BCLK
DATA
Figure 7. DAC Packed Mode 256
AD1836
REV. PrC
–11–
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AD1836.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD1833 | Multichannel 24-Bit/ 192 kHz/ DAC | Analog Devices |
| AD1833A | 24-Bit/ 192 kHz/ DAC | Analog Devices |
| AD1835 | 2 ADC/ 8 DAC/ 96 kHz/ 24-Bit Codec | Analog Devices |
| AD1835A | Codecs | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |