PDF AD1674 Data sheet ( Hoja de datos )

Número de pieza	AD1674
Descripción	12-Bit 100 kSPS A/D Converter
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES Complete Monolithic 12-Bit 10 ␮s Sampling ADC On-Board Sample-and-Hold Amplifier Industry Standard Pinout 8- and 16-Bit Microprocessor Interface AC and DC Specified and Tested Unipolar and Bipolar Inputs ؎5 V, ؎10 V, 0 V–10 V, 0 V–20 V Input Ranges Commercial, Industrial and Military Temperature Range Grades MIL-STD-883 and SMD Compliant Versions Available 12-Bit 100 kSPS A/D Converter AD1674* FUNCTIONAL BLOCK DIAGRAM 12/8 CS A0 CE R/C REF OUT 10V REF CONTROL CLOCK SAR 12 AGND 20k REF IN BIP OFF 20VIN 10VIN 5k 2.5k 5k COMP 12 10k 10k DAC IDAC 5k 2.5k SHA AD1674 STS DB11 (MSB) 12 DB0 (LSB) PRODUCT DESCRIPTION The AD1674 is a complete, multipurpose, 12-bit analog-to- digital converter, consisting of a user-transparent onboard sample-and-hold amplifier (SHA), 10 volt reference, clock and three-state output buffers for microprocessor interface. The AD1674 is pin compatible with the industry standard AD574A and AD674A, but includes a sampling function while delivering a faster conversion rate. The on-chip SHA has a wide input bandwidth supporting 12-bit accuracy over the full Nyquist bandwidth of the converter. The AD1674 is fully specified for ac parameters (such as S/(N+D) ratio, THD, and IMD) and dc parameters (offset, full-scale error, etc.). With both ac and dc specifications, the AD1674 is ideal for use in signal processing and traditional dc measure- ment applications. The AD1674 design is implemented using Analog Devices’ BiMOS II process allowing high performance bipolar analog cir- cuitry to be combined on the same die with digital CMOS logic. Five different temperature grades are available. The AD1674J and K grades are specified for operation over the 0°C to +70°C temperature range. The A and B grades are specified from –40°C to +85°C; the AD1674T grade is specified from –55°C to +125°C. The J and K grades are available in both 28-lead plastic DIP and SOIC. The A and B grade devices are available in 28-lead hermetically sealed ceramic DIP and 28-lead SOIC. The T grade is available in 28-lead hermetically sealed ceramic DIP. *Protected by U. S. Patent Nos. 4,962,325; 4,250,445; 4,808,908; RE30586 . PRODUCT HIGHLIGHTS 1. Industry Standard Pinout: The AD1674 utilizes the pinout established by the industry standard AD574A and AD674A. 2. Integrated SHA: The AD1674 has an integrated SHA which supports the full Nyquist bandwidth of the converter. The SHA function is transparent to the user; no wait-states are needed for SHA acquisition. 3. DC and AC Specified: In addition to traditional dc specifica- tions, the AD1674 is also fully specified for frequency do- main ac parameters such as total harmonic distortion, signal-to-noise ratio and input bandwidth. These parameters can be tested and guaranteed as a result of the onboard SHA. 4. Analog Operation: The precision, laser-trimmed scaling and bipolar offset resistors provide four calibrated ranges: 0 V to +10 V and 0 V to +20 V unipolar, –5 V to +5 V and –10 V to +10 V bipolar. The AD1674 operates on +5 V and ± 12 V or ± 15 V power supplies. 5. Flexible Digital Interface: On-chip multiple-mode three-state output buffers and interface logic allow direct connection to most microprocessors. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 1 page AD1674 (for all grades TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%, SWITCHING SPECIFICATIONS VLOGIC = +5 V ؎10%, VEE = –15 V ؎ 10% or –12 V ؎ 5%; VIL = 0.4 V, VIH = 2.4 V unless otherwise noted) CONVERTER START TIMING (Figure 1) Parameter J, K, A, B, Grades T Grade Symbol Min Typ Max Min Typ Max Units Conversion Time 8-Bit Cycle 12-Bit Cycle STS Delay from CE tC tC tDSC CE Pulse Width tHEC CS to CE Setup tSSC CS Low During CE High tHSC R/C to CE Setup tSRC R/C Low During CE High tHRC A0 to CE Setup tSAC A0 Valid During CE High tHAC 7 9 50 50 50 50 50 0 50 8 7 8 µs 10 9 10 µs 200 225 ns 50 ns 50 ns 50 ns 50 ns 50 ns 0 ns 50 ns READ TIMING—FULL CONTROL MODE (Figure 2) Parameter J, K, A, B, Grades T Grade Symbol Min Typ Max Min Typ Max Units CE tHEC __ CS tHSC tSSC _ R/C tSRC tHRC A0 tSAC tHAC tC STS DB11 – DB0 tDSC HIGH IMPEDANCE Figure 1. Converter Start Timing Access Time tDD1 Data Valid After CE Low tHD Output Float Delay CS to CE Setup R/C to CE Setup A0 to CE Setup CS Valid After CE Low R/C High After CE Low A0 Valid After CE Low tHL5 tSSR tSRR tSAR tHSR tHRR tHAR 75 150 75 150 ns 252 252 ns 203 154 ns 150 150 ns 50 50 ns 0 0 ns 50 50 ns 0 0 ns 0 0 ns 50 50 ns NOTES 1tDD is measured with the load circuit of Figure 3 and is defined as the time required for an output to cross 0.4 V or 2.4 V. 20°C to TMAX. 3At –40°C. 4At –55°C. 5tHL is defined as the time required for the data lines to change 0.5 V when loaded with the circuit of Figure 3. All min and max specifications are guaranteed. Specifications subject to change without notice. Test VCP COUT _C_E CS tSSR tHSR _ R/C tSSR tHRR A0 tSAR tHAR STS DB11 – DB0 HIGH IMPEDANCE tHS tHD DATA VALID tDD tHL Figure 2. Read Timing Access Time High Z to Logic Low Float Time Logic High to High Z Access Time High Z to Logic High Float Time Logic Low to High Z 5V 0V 0V 5V 100 pF 10 pF 100 pF 10 pF IOL HIGH IMP. DOUT COUT VCP IOH Figure 3. Load Circuit for Bus Timing Specifications REV. C –5– 5 Page AD1674 –15V R1 100k +15V 100k 100Ω R2 100Ω 0 TO +10V ANALOG INPUTS 0 TO +20V 2 12/8 STS 28 3 CS 4 A0 5 R/C 6 CE 10 REF IN 8 REF OUT 12 BIP OFF HIGH BITS 24-27 MIDDLE BITS 20-23 LOW BITS 16-19 AD1674 +5V 1 13 10VIN +15V 7 14 20VIN –15V 11 9 ANA COM DIG COM 15 Figure 11. Unipolar Input Connections with Gain and Offset Trims The full-scale trim is done by applying a signal 1 1/2 LSB below the nominal full scale (9.9963 V for a 10 V range) and adjusting R2 until the last transition is located (1111 1111 1110 to 1111 1111 1111). If full-scale adjustment is not required, R2 should be replaced with a fixed 50 Ω ± 1% metal film resistor. If REF OUT is connected directly to REF IN, the additional full-scale error will be approximately 1%. BIPOLAR RANGE INPUTS The connections for the bipolar-input mode are shown in Figure 12. Either or both of the trimming potentiometers can be replaced with 50 Ω ± 1% fixed resistors if the specified AD1674 accuracy limits are sufficient for the application. If the pins are shorted together, the additional offset and gain errors will be approximately 1%. To trim bipolar offset to its nominal value, apply a signal 1/2 LSB below midrange (–1.22 mV for a ± 5 V range) and adjust R1 until the major carry transition is located (0111 1111 1111 to 1000 0000 0000). To trim the full-scale error, apply a signal 1 1/2 LSB below full scale (+4.9963 V for a ± 5 V range) and adjust R2 to give the last positive transition (1111 1111 1110 to 1111 1111 1111). These trims are interactive so several itera- tions may be necessary for convergence. A single-pass calibration can be done by substituting a negative full-scale trim for the bipolar offset trim (error at midscale), using the same circuit. First, apply a signal 1/2 LSB above minus full scale (–4.9988 V for a ±5 V range) and adjust R1 until the minus full-scale transition is located (0000 0000 0001 to 0000 0000 0000). Then perform the gain error trim as outlined above. R2 100Ω ±5V ANALOG INPUTS ±10V R1 100Ω 2 12/8 3 CS 4 A0 5 R/C 6 CE 10 REF IN 8 REF OUT 12 BIP OFF STS 28 HIGH BITS 24-27 MIDDLE BITS 20-23 LOW BITS 16-19 AD1674 +5V 1 13 10VIN 14 20VIN 9 ANA COM +15V 7 –15V 11 DIG COM 15 Figure 12. Bipolar Input Connections with Gain and Offset Trims REFERENCE DECOUPLING It is recommended that a 10 µF tantalum capacitor be con- nected between REF IN (Pin 10) and ground. This has the effect of improving the S/(N+D) ratio through filtering possible broad-band noise contributions from the voltage reference. BOARD LAYOUT Designing with high resolution data converters requires careful attention to board layout. Trace impedance is a significant issue. At the 12-bit level, a 5 mA current through a 0.5 Ω trace will develop a voltage drop of 2.5 mV, which is 1 LSB for a 10 V full-scale range. In addition to ground drops, inductive and ca- pacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital sig- nals. Finally, power supplies should be decoupled in order to filter out ac noise. The AD1674 has a wide bandwidth sampling front end. This means that the AD1674 will “see” high frequency noise at the input, which nonsampling (or limited-bandwidth sampling) ADCs would ignore. Therefore, it’s important to make an effort to eliminate such high frequency noise through decoupling or by using an anti-aliasing filter at the analog input of the AD1674. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recom- mended to provide low impedance signal paths. Separate analog and digital ground planes are also desirable, with a single inter- connection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them (if necessary) only at right angles. The AD1674 incorporates several features to help the user’s lay- out. Analog pins are adjacent to help isolate analog from digital signals. Ground currents have been minimized by careful circuit architecture. Current through AGND is 2.2 mA, with little code-dependent variation. The current through DGND is domi- nated by the return current for DB11–DB0. SUPPLY DECOUPLING The AD1674 power supplies should be well filtered, well regu- lated, and free from high frequency noise. Switching power sup- plies are not recommended due to their tendency to generate spikes which can induce noise in the analog system. Decoupling capacitors should be used in very close layout prox- imity between all power supply pins and ground. A 10 µF tanta- lum capacitor in parallel with a 0.1 µF disc ceramic capacitor provides adequate decoupling over a wide range of frequencies. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD1674, associated analog input circuitry, and interconnec- tions as far as possible from logic circuitry. A solid analog ground plane around the AD1674 will isolate large switching ground currents. For these reasons, the use of wire-wrap circuit construction is not recommended; careful printed-circuit con- struction is preferred. REV. C –11– 11 Page

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