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AD1672 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1672
Beschreibung Complete 12-Bit/ 3 MSPS Monolithic A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD1672 Datasheet, Funktion
a
Complete 12-Bit, 3 MSPS
Monolithic A/D Converter
AD1672
FEATURES
Single Supply
Pin Configurable Input Voltage Ranges
Power Dissipation: 240 mW
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.5 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 68 dB
Spurious-Free Dynamic Range: –77 dB
Out of Range Indicator
Binary Output Data
Digital I/Os Compatible with +5 V or +3.3 V Logic
28-Pin PLCC Package
PRODUCT DESCRIPTION
The AD1672 is a monolithic, single supply 12-bit, 3 MSPS
analog-to-digital converter with an on-chip, high performance
sample-and-hold amplifier (SHA) and voltage reference. The
AD1672 uses a multistage pipelined architecture with output
error correction logic to provide 12-bit accuracy at 3 MSPS data
rates and guarantees no missing codes over the full operating
temperature range. The AD1672 combines a high performance
BiCMOS process and a novel architecture to achieve its high
performance levels.
The fast settling input SHA is equally suited for both multi-
plexed systems that switch negative to positive full-scale voltage
levels in successive channels and sampling single-channel inputs
at frequencies up to the Nyquist rate. The AD1672’s wideband
input combined with the power and cost savings over previously
available solutions will enable new designs in communications,
imaging and medical applications. The AD1672 provides both
reference output and reference input pins allowing the onboard
reference to serve as a system reference. An external reference
can also be chosen to suit the dc accuracy and temperature drift
requirements of the application. The digital output data is pre-
sented in a straight binary output format for the unipolar input
ranges of 0 V to 2.5 V and 0 V to 5.0 V. For the bipolar input
range of –2.5 V to +2.5 V, the digital output data is presented in
an offset binary format. An out-of-range (OTR) signal indicates
an overflow condition. It can be used with the most significant
bit to determine low or high overflow.
The AD1672 is packaged in a 28-pin PLCC package and is
specified for operation from –40°C to +85°C.
PRODUCT HIGHLIGHT
The AD1672 offers a complete single-chip sampling 12-bit,
3 MSPS analog-to-digital conversion function in a 28-pin
PLCC package.
The AD1672 at 240 mW consumes a fraction of the power of
presently available solutions and provides exceptional perfor-
mance relative to other monolithic solutions.
OUT OF RANGE (OTR)—The OTR output bit indicates
when the input signal is beyond the AD1672’s input range.
Ease-of-Use—The single supply AD1672 is complete with SHA
voltage reference and pin strappable input ranges. It is compat-
ible with a wide range of amplifiers.
FUNCTIONAL BLOCK DIAGRAM
AIN1 & 2
REF IN
REFCOM
NOISE
REDUCTION
2.5V REF
OUTPUT
REF
AMP
DAC
AMP
BANDGAP
REFERENCE
REFCOM
AD1672
THA
ADC DAC
THA
ADC DAC
THA
ADC DAC
THA
ADC
44 34
CORRECTION LOGIC
LATCHES
CLOCK TIMER
OUTPUT DATA
12 BITS
CLOCK INPUT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD1672 Datasheet, Funktion
AD1672
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Integral nonlinearity error refers to the deviation of each individual
code from a line drawn from “negative full scale” through
“positive full scale.” The point used as “negative full scale”
occurs 1/2 LSB before the first code transition (all zeros to only
the LSB on). “Positive full scale” is defined as a level 1 1/2 LSB
beyond the last code transition (to all ones). The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. Guaranteed no missing codes to
12-bit resolution indicates that all 4096 codes must be present
over all operating ranges.
UNIPOLAR OFFSET ERROR
In the unipolar mode, the first transition should occur at a level
1/2 LSB above analog common. Unipolar offset is defines as
the deviation of the actual from that point.
BIPOLAR ZERO ERROR
In the bipolar mode, the major carry transition should occur for
an analog value 1/2 LSB below analog common. Zero error is
defined as the deviation of the actual transition from that point.
GAIN ERROR
The first transition should occur for an analog value 1/2 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 1/2 LSB below the nominal full
scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between first and last code transitions.
POWER SUPPLY REJECTION
One of the effects of power supply error on the performance of
the device will be a small change in gain. The specifications
show the maximum change in the converter’s full scale as the
supplies are varied from minimum to maximum values.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
CODE TRANSITION NOISE
The effects of noise are to introduce an uncertainty in the pre-
cise determination of the analog input values at which the out-
put code transitions take place, and, in effect, to increase or
reduce the quantization band. Code transition noise describes
the quantization band variation resulting from noise in terms of
rms LSBs.
APERTURE DELAY
Aperture delay is a measure of the Sample-and-Hold (SHA)
performance and is measured from the rising edge of the clock
input to when the input signal is held for conversion.
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
DYNAMIC SPECIFICATIONS
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of
mfa ± nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms
are those for which m or n is not equal to zero. For example,
the second order terms are (fa + fb) and (fa – fb) and the third
order terms are (2 fa + fb), (2 fa – fb), (fa + 2fb) and (2 fb – fa).
The IMD products are expressed as the decibel ratio of the rms
sum of the measured input signals to the rms sum of the distor-
tion terms. The two signals are of equal amplitude and the peak
value of their sums is –0.5 dB from full-scale. The IMD prod-
ucts are normalized to a 0 dB input signal.
FULL-POWER BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
SPURIOUS FREE DYNAMIC RANGE
The difference, in dB, between the rms amplitude of the input
signal and the peak spurious signal.
–6– REV. 0

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AD1672 pdf, datenblatt
AD1672
The AD1672’s CMOS digital output drivers can be configured
to interface with +5 V or +3.3 V logic families by setting
DRVDD to +5 V or +3.3 V respectively . They are also sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause glitches
on the supplies and may effect S/(N+D) performance. Applica-
tions requiring the AD1672 to drive large capacitive loads or
large fanout may require additional decoupling capacitors on
DRVDD and DVDD. In extreme cases, external buffers or
latches may be required.
OUT OF RANGE
An out-of-range condition exists when the analog input voltage
is beyond the input range (0 V to +2.5 V, 0 V to +5.0 V, ± 2.5 V)
of the converter. OTR (Pin 15) is a digital output which is up-
dated along with the data output pertaining to the particular
sampled analog input voltage. Hence, OTR has the same pipe-
line delay (latency) as the digital data. It is set low when the
analog input voltage is within the analog input range. It is set
HIGH and will remain HIGH when the analog input voltage
exceeds the input range by typically 1/2 LSB from the center of
the ± full-scale output codes. OTR will remain HIGH until the
analog input is within the input range and another conversion is
completed. By logical ANDing OTR with the MSB and its
complement, overrange high or underrange low conditions can
be detected. Table IV is a truth table for the over/under range
circuit in Figure 20 which uses NAND gates. Systems requir-
ing programmable gain conditioning prior to the AD1672 can
immediately detect an out-of-range condition, thus eliminating
gain selection iterations. Also, OTR can be used for digital off-
set and gain calibration (see Gain and Offset Adjustment).
OTR
0
0
1
1
Table VI. Out-of-Range Truth Table
MSB
Analog Input Is
0 In Range
1 In Range
0 Underrange
1 Overrange
MSB
OTR
LSB
OVER = “1”
UNDER = “1”
+5V
6MHz
R
DQ
Q
S
+5V
CLK
3MHz
Figure 22. Divide-by-Two Clock Circuit
In this case, a 6 MHz clock is divided by 2 to produce the 3 MHz
clock input for the AD1672. In this configuration, the duty
cycle of the 6 MHz clock is irrelevant.
The input circuitry for the CLOCK pin is designed to accom-
modate CMOS inputs. The quality of the logic input, particu-
larly the rising edge, is critical in realizing the best possible jitter
performance for the part: the faster the rising edge, the better
the jitter performance.
The offset of the AD1672 is sensitive to the rising edge (i.e.,
dV/dt) seen at CLOCK due to clock feedthrough. An addi-
tional offset component becomes noticeable for rise times below
10 ns and causes an additional few LSBs of offset. The amount
of additional offset is dependent on dV/dt of the rising edge and
hence will remain constant for nonvarying rising edges. For
applications which are sensitive to a change in offset due to a
variation in the rise edge, the CLOCK rise time may be reduced
by selecting a slower logic family or installing a 1 kresistor be-
tween the clock driver and CLOCK of the AD1672.
As a result, careful selection of the logic family for the clock
driver, as well as the fanout and capacitive load on the clock
line, is important. Jitter-induced errors become more predomi-
nant at higher frequency, large amplitude inputs, where the
input slew rate is greatest.
Although the AD1672 is designed to support a sampling rate of
3 MSPS, operating at slightly faster or slower clock rates may be
possible with a minimum degradation in performance levels. Fig-
ure 23 is a plot of the S/(N+D) vs. clock frequency for a 500 kHz
analog input. In fact, the AD1672 is capable of operating with
a clock frequency as low as 20 kHz
75
70
Figure 21. Overrange or Underrange Logic
CLOCK INPUT
The AD1672 internal timing control uses the two edges of the
clock input to generate a variety of internal timing signals. The
clock input must meet or exceed the minimum specified pulse
width high and low (tCH and tCL) specifications of 167 ns to
maintain the AD1672’s rated performance. At a clock rate of
3 MSPS, the clock input must have a 50% duty cycle to meet
this timing requirement. For clock rates below 3 MSPS, the
duty cycle may deviate from 50% to the extent that both tch and
tcl are satisfied. One way to minimize the tolerance of a 50%
duty cycle clock is to divide down a clock of higher frequency,
as shown in Figure 22.
65
60
55
50
0 0.5 1 1.5 2 2.5
3 3.5
FREQUENCY – MHz
4 4.5
5
Figure 23. Typical S/(N+D) vs. Clock Frequency;
fIN = 500 kHz, Full-Scale Input
–12–
REV. 0

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