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AD14160L Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD14160L
Beschreibung Quad-SHARC DSP Multiprocessor Family
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 52 Seiten
AD14160L Datasheet, Funktion
a
PERFORMANCE FEATURES
ADSP-21060 Core Processor (. . . ؋4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Sixteen 40 Mbyte/s Link Ports (Four per SHARC)
Eight 40 Mbit/s Independent Serial Ports (Two
from Each SHARC)
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
452-Lead Ceramic Ball Grid Array (CBGA)
1.85" (47 mm) Body Size
0.200" Max Height
0.050" Ball Pitch
29 Grams (typical)
JC = 0.36؇C/W
Quad-SHARC®
DSP Multiprocessor Family
AD14160/AD14160L
FUNCTIONAL BLOCK DIAGRAM
ID2-0
CPA
SPORT 1
SPORT 0
TDI
SHARC_A
LINK 0
LINK 5
TDO
LINK 0
LINK 5
TDI
SHARC_B
ID2-0
CPA
SPORT 1
SPORT 0
AD14160/
AD14160L
SHARC BUS (ADDR31-0, DATA47-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR6-1, RPBA, DMAR1.2, DMAG1.2)
ID2-0
CPA SHARC_D
SPORT 1
SPORT 0
TDO
LINK 0
LINK 5
TDI
LINK 0 SHARC_C
LINK 5
TDO
ID2-0
CPA
SPORT 1
SPORT 0
GENERAL DESCRIPTION
The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid
Array (CBGA) puts the power of the first generation AD14060
(CQFP) DSP multiprocessor into a very high density ball grid
array package; now with additional link and serial I/O pinned
out, beyond that from the CQFP package. The core of the multi-
processor is the ADSP-21060 DSP microcomputer. The AD14x60
modules have the highest performance—density and lowest
cost— performance ratios of any in their class. They are ideal
for applications requiring higher levels of performance and/or
functionality per unit area.
The AD14160/AD14160L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, links connect the SHARC
in a ring. Externally, each SHARC has a total of 160 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
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REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998






AD14160L Datasheet, Funktion
AD14160/AD14160L
Link port 4, the boot link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link port booting is possible as described under “Link
Port Booting.”
Link port data is packed into 32-bit or 48-bit words, and can be
directly read by the SHARC core processor or DMA-transferred
to on-SHARC memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
Serial Ports
The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices. Each
SHARC has two serial ports. All eight of the AD14160/AD14160L
serial ports are brought off-module.
The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s. Inde-
pendent transmit and receive functions provide more flexible
communications. Serial port data can be automatically trans-
ferred to and from on-SHARC memory via DMA, and each of
the serial ports offers time division multiplexed (TDM) multi-
channel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
Program Booting
The AD14160/AD14160L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers four options for program booting: 1) from an 8-bit
EPROM; 2) from a host processor; 3) through the link ports;
and 4) no-boot. In no-boot mode, the SHARC starts executing
instructions from address 0x0040 0004 in external memory.
The boot mode is selected by the state of the following signals:
BMS, EBOOT, and LBOOT.
On the AD14160/AD14160L, SHARC_A’s boot mode is sepa-
rately controlled, while SHARCs B, C, and D are controlled as
a group. With this flexibility, the AD14160/AD14160L can be
configured to boot in any of the following methods.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each
ADSP-21060 must have its EBOOT, LBOOT and BMS pins
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS = 1. After system power-up, each ADSP-21060 will be in
the idle state and the BRx bus request lines will be deasserted.
The host must assert the HBR input and boot each ADSP-21060
by asserting its CS pin and downloading instructions.
Multiprocessor EPROM Booting
There are two methods of booting the multiprocessor system
from an EPROM.
SHARC_A Is Booted, Which Then Boots the Others. The
EBOOT pin on the SHARC_A must be set high for EPROM
booting. All other ADSP-21060s should be configured for host
booting (EBOOT = 0, LBOOT = 0, and BMS = 1), which
leaves them in the idle state at start-up and allows SHARC_A
to become bus master and boot itself. Only the BMS pin of
SHARC_A is connected to the chip select of the EPROM.
When SHARC_A has finished booting, it can boot the re-
maining ADSP-21060s by writing to their external port DMA
buffer 0 (EPB0) via multiprocessor memory space.
All ADSP-21060s Boot in Turn From a Single EPROM.
The BMS signals from each ADSP-21060 may be wire-ORed
together to drive the chip select pin of the EPROM. Each
ADSP-21060 can boot in turn, according to its priority. When
the last one has finished booting, it must inform the others (which
may be in the idle state) that program execution can begin.
Multiprocessor Link Port Booting
Booting can also be accomplished from a single source through
the link ports. Link Buffer 4 must always be used for booting.
To simultaneously boot all of the ADSP-21060s, a parallel
common connection is available through Link Port 4 on each of
the processors. Or, using the daisy chain connection that exists
between the processors’ link ports, each ADSP-21060 can boot
the next one in turn. In this case, the Link Assignment Register
(LAR) must be programmed to configure the internal link ports
with Link Buffer 4.
Multiprocessor Booting From External Memory
If external memory contains a program after reset, then
SHARC_A should be set up for no boot mode; it will begin ex-
ecuting from address 0x0040 0004 in external memory. When
booting has completed, the other ADSP-21060s may be booted
by SHARC_A if they are set up for host booting, or they can
begin executing out of external memory if they are set up for no
boot mode. Multiprocessor bus arbitration will allow this booting
to occur in an orderly manner.
Host Processor Interface
The AD14160/AD14160L’s host interface allows for easy con-
nection to standard microprocessor buses, both 16-bit and 32-
bit, with little additional hardware required. Asynchronous
transfers at speeds up to the full clock rate of the module are
supported. The host interface is accessed through the AD14160/
AD14160L external port and is memory-mapped into the uni-
fied address space. Four channels of DMA are available for the
host interface; code and data transfers are accomplished with
low software overhead.
The host processor requests the AD14160/AD14160L’s external
bus with the host bus request (HBR), host bus grant (HBG),
and ready (REDY) signals. The host can directly read and write
the internal memory of the SHARCs, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
Direct Memory Access (DMA) Controller
The SHARCs on-chip DMA control logic allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to each SHARCs
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions.
DMA transfers can occur between SHARC internal memory
and either external memory, external peripherals, or a host
processor. DMA transfers can also occur between the SHARC’s
internal memory and its serial ports or link ports. DMA trans-
fers between external memory and external peripheral devices are
another option. External bus packing to 16-, 32- or 48-bit words
is performed during DMA transfers.
–6– REV. A

6 Page









AD14160L pdf, datenblatt
AD14160/AD14160L
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and con-
trol the target board processor during emulation. The EZ-ICE
probe requires that the AD14160/AD14160L’s CLKIN (op-
tional), TMS, TCK, TRST, TDI, TDO, EMU and GND signals
be made accessible on the target system via a 14-pin connector
(a pin strip header) such as that shown in Figure 6. The EZ-
ICE probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The
length of the traces between the connector and the AD14160/
AD14160L’s JTAG pins should be as short as possible.
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
1
3
5
7
9
9
11
GND
13
2
EMU
4
CLKIN (OPTIONAL)
6
TMS
8
TCK
10
TRST
12
TDI
14
TDO
TOP VIEW
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
Emulator (Jumpers in Place)
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location;
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The BTMS, BTCK, BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 6. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted after power-up (through
BTRST on the connector) or held low for proper operation of
the AD14160/AD14160L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal Termination
TMS
TCK
TRST
TDI
TDO
CLKIN
EMU
Driven through 22 Resistor (16 mA/3.2 mA Driver)
Driven at 10 MHz through 22 Resistor (16 mA/
3.2 mA Driver)
Driven by Open-Drain Driver* (Pulled Up by On-Chip
20 kResistor)
Driven by 16 mA/3.2 mA Driver
One TTL Load, No Termination
One TTL Load, No Termination (Optional Signal)
4.7 kPull-Up Resistor, One TTL Load (Open-Drain
Output from ADSP-2106x)
*TRST is driven low until the EZ-ICE probe is turned on by the EZ-ICE
software (after the invocation command).
Figure 7 shows JTAG scan path connections for the multi-
processor system.
OTHER
JTAG
CONTROLLER
SHARC_A
TDI
EZ-ICE
JTAG
CONNECTOR
TDI
TDO
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
SHARC_B
TDI TDO
SHARC_C
TDI TDO
SHARC_D
TDI TDO
JTAG DEVICE
(OPTIONAL)
TDI TDO
Figure 7. JTAG Scan Path Connections for the AD14160/AD14160L
ADSP-2106x
#n
TDI TDO
–12–
REV. A

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