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PDF AD14060L Data sheet ( Hoja de datos )
| Número de pieza | AD14060L | |
| Descripción | Quad-SHARC DSP Multiprocessor Family | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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PERFORMANCE FEATURES
ADSP-21060 core processor ( × 4)
480 MFLOPS peak, 320 MFLOPS sustained
25 ns instruction rate, single-cycle
instruction execution—each of four processors
16 Mbit shared SRAM (internal to SHARCs)
4 gigawords addressable off-module memory
Twelve 40 Mbyte/s link ports (3 per SHARC)
Four 40 Mbit/s independent serial ports
(one from each SHARC)
One 40 Mbit/s common serial port
5 V and 3.3 V operation
32-bit single precision and 40-bit extended
precision IEEE floating point data formats, or
32-bit fixed point data format
IEEE JTAG Standard 1149.1 test access port and
on-chip emulation
PACKAGING FEATURES
308-lead ceramic quad flatpack (CQFP)
2.05" (52 mm) body size
Cavity up or down, configurable
Low profile, 0.160" height
Hermetic
25 Mil (0.65 mm) lead pitch
29 grams (typical)
θJC = 0.36°C/W
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer. The
AD14060/AD14060L has the highest performance-to-density
and lowest cost-to-performance ratios of any in its class. It is
ideal for applications requiring higher levels of performance
and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve
480 peak MFLOPS with a single chip type in a single package.
The on-chip SRAM of the DSPs provides 16 Mbits of on-
module shared SRAM. The complete shared bus (48 data,
Quad-SHARC®
DSP Multiprocessor Family
AD14060/AD14060L
FUNCTIONAL BLOCK DIAGRAM
CPA
SPORT 1
TDI SHARC_A
(ID2–0 = 1)
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
SHARC_B
(ID2–0 = 2)
CPA
SPORT 1
SSHWA,RACCKB, USBST(SA, DHDBRR3, 1H–B0G, D, RAETDAY4,7, –B0R,6M–1S,3R-0P,BRAD,,DWMRA,RP1A.2G,ED,MAADGR1C.L2K) ,
SHARC_D
CPA
(ID2–0 = 4)
SPORT 1
TDO
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
SHARC_C
(ID2–0 = 3)
CPA
SPORT 1
AD14060/AD14060L
Figure 1.
00667-001
32 address) is also brought off-module for interfacing with
expansion memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide direct
communication among the four SHARCs, as well as high speed
off-module access. Internally, each SHARC has a direct link port
connection. Externally, each SHARC has a total of 120 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and
optimized signal routing lengths and separation. The fully
tested and ready-to-insert multiprocessor also significantly
reduces board space.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD14060/AD14060L
TIMING SPECIFICATIONS
This data sheet represents production-released specifications
for the AD14060 (5 V), and for the AD14060L (3.3 V). The
ADSP-21060 die components are 100% tested, and the
assembled AD14060/AD14060L units are again extensively
tested at speed and across temperature. Parametric limits were
established from the ADSP-21060 characterization followed by
further design and analysis of the AD14060/AD14060L package
characteristics.
The specifications are based on a CLKIN frequency of 40 MHz
(tCK = 25 ns). The DT derating allows specifications at other
CLKIN frequencies (within the minimum to maximum range
of the tCK specification; see Table 3). DT is the difference
between the actual CLKIN period and a CLKIN period of 25 ns:
DT = tCK − 25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, one
cannot meaningfully add parameters to derive longer times.
Switching Characteristics specify how the processor changes its
signals. The user has no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics
specify what the processor does in a given circumstance. The
user can also use switching characteristics to ensure that any
timing requirement of a device connected to the processor
(such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
Table 3. Clock Input
Parameter
Clock Input
Timing Requirements:
tCK CLKIN Period
tCKL CLKIN Width Low
tCKH CLKIN Width High
tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V)
40 MHz (5 V)
Min Max
25 100
7
5
3
40 MHz (3.3 V)
Min Max
25 100
9.5
5
3
Unit
ns
ns
ns
ns
CLKIN
tCK
tCKH
tCKL
Figure 2. Clock Input
Rev. B | Page 5 of 48
5 Page 
CLKIN
ADRCLK
ADDRESS
SW
tDADCCK
tDADRO
tADRCKH
tDAAK
tADRCK
tADRCKL
tHADRO
PAGE
ACK
(IN)
tDPGC
tSACKC
tHACKC
READ CYCLE
RD
DATA
(IN)
WRITE CYCLE
WR
DATA
(OUT)
tDRWL
tDRDO
tSSDATI tHSDATI
tDRWL
tDWRO
tSDDATO
tDATTR
Figure 9. Synchronous Read/Write—Bus Master
AD14060/AD14060L
Rev. B | Page 11 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD14060L.PDF ] | |
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