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AD14060 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD14060
Beschreibung Quad-SHARC DSP Multiprocessor Family
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD14060 Datasheet, Funktion
PERFORMANCE FEATURES
ADSP-21060 core processor ( × 4)
480 MFLOPS peak, 320 MFLOPS sustained
25 ns instruction rate, single-cycle
instruction execution—each of four processors
16 Mbit shared SRAM (internal to SHARCs)
4 gigawords addressable off-module memory
Twelve 40 Mbyte/s link ports (3 per SHARC)
Four 40 Mbit/s independent serial ports
(one from each SHARC)
One 40 Mbit/s common serial port
5 V and 3.3 V operation
32-bit single precision and 40-bit extended
precision IEEE floating point data formats, or
32-bit fixed point data format
IEEE JTAG Standard 1149.1 test access port and
on-chip emulation
PACKAGING FEATURES
308-lead ceramic quad flatpack (CQFP)
2.05" (52 mm) body size
Cavity up or down, configurable
Low profile, 0.160" height
Hermetic
25 Mil (0.65 mm) lead pitch
29 grams (typical)
θJC = 0.36°C/W
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer. The
AD14060/AD14060L has the highest performance-to-density
and lowest cost-to-performance ratios of any in its class. It is
ideal for applications requiring higher levels of performance
and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve
480 peak MFLOPS with a single chip type in a single package.
The on-chip SRAM of the DSPs provides 16 Mbits of on-
module shared SRAM. The complete shared bus (48 data,
Quad-SHARC®
DSP Multiprocessor Family
AD14060/AD14060L
FUNCTIONAL BLOCK DIAGRAM
CPA
SPORT 1
TDI SHARC_A
(ID2–0 = 1)
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
SHARC_B
(ID2–0 = 2)
CPA
SPORT 1
SSHWA,RACCKB, USBST(SA, DHDBRR3, 1H–B0G, D, RAETDAY4,7, –B0R,6M–1S,3R-0P,BRAD,,DWMRA,RP1A.2G,ED,MAADGR1C.L2K) ,
SHARC_D
CPA
(ID2–0 = 4)
SPORT 1
TDO
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
SHARC_C
(ID2–0 = 3)
CPA
SPORT 1
AD14060/AD14060L
Figure 1.
00667-001
32 address) is also brought off-module for interfacing with
expansion memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide direct
communication among the four SHARCs, as well as high speed
off-module access. Internally, each SHARC has a direct link port
connection. Externally, each SHARC has a total of 120 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and
optimized signal routing lengths and separation. The fully
tested and ready-to-insert multiprocessor also significantly
reduces board space.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD14060 Datasheet, Funktion
AD14060/AD14060L
Table 4. Reset
Parameter
Reset
Timing Requirements:
tWRST RESET Pulse Width Low1
tSRST RESET Setup before CLKIN High2
5V
Min Max
4 tCK
14 + DT/2
tCK
3.3 V
Min Max
4 tCK
14 + DT/2
tCK
Unit
ns
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of the external clock oscillator).
2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (that is, for a SIMD system). Not required for
multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
RESET
Table 5. Interrupts
Parameter
Interrupts
Timing Requirements:
tSIR IRQ2-0 Setup before CLKIN High1
tHIR IRQ2-0 Hold before CLKIN High1
tIPW IRQ2-0 Pulse Width2
1 Only required for IRQx recognition in the following cycle.
2 Applies only if tSIR and tHIR requirements are not met.
tWRST
Figure 3. Reset
tSRST
5V
Min Max
3.3 V
Min Max
Unit
18 + 3 DT/4
2 + tCK
11.5 + 3 DT/4
18 + 3 DT/4
2 + tCK
11.5 + 3 DT/4
ns
ns
ns
CLKIN
IRQ2–0
tSIR
tHIR
tIPW
Figure 4. Interrupts
Rev. B | Page 6 of 48

6 Page









AD14060 pdf, datenblatt
AD14060/AD14060L
SYNCHRONOUS READ/WRITE—BUS SLAVE
Use these specifications for bus master access to a slave’s IOP registers or internal memory in multiprocessor memory space. The bus
master must meet these bus slave timing requirements.
Table 11. Specifications
Parameter
Timing Requirements:
tSADRI
Address, SW Setup before CLKIN
tHADRI
Address, SW Hold before CLKIN
tSRWLI
RD/WR Low Setup before CLKIN1
tHRWLI
RD/WR Low Hold after CLKIN
tRWHPI
RD/WR Pulse High
tSDATWH Data Setup before WR High
tHDATWH Data Hold after WR High
Switching Characteristics:
tSDDATO
tDATTR
tDACKAD
Data Delay after CLKIN
Data Disable after CLKIN2
ACK Delay after Address, SW3
tACKTR
ACK Disable after CLKIN3
5V
Min Max
15.5 + DT/2
9.5 + 5 DT/16
−3.5 − 5 DT/16
3
5.5
1.5
4.5 + DT/2
+8 + 7 DT/16
0 − DT/8
−1 − DT/8
20 + 5 DT/16
8 − DT/8
10
+7 − DT/8
3.3 V
Min Max
Unit
15.5 + DT/2
9.5 + 5 DT/16
−3.25 − 5 DT/16
3
5.5
1.5
4.5 + DT/2
+8 + 7 DT/16
ns
ns
ns
ns
ns
ns
ns
0 − DT/8
−1 − DT/8
20.25 + 5 DT/16
8 − DT/8
10
+7 − DT/8
ns
ns
ns
ns
1 tSRWLI (min) = 9.5 + 5 DT/16 when the multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min) =
4 + DT/8.
2 See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
3 tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3 DT/4. If the address and SW inputs have
setup times greater than 19 + 3 DT/4, then ACK is valid 15 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match responds with ACK regardless
of the state of MMSWS or strobes. A slave three-states ACK every cycle with tACKTR.
CLKIN
ADDRESS
SW
ACK
READ ACCESS
RD
DATA
(OUT)
WRITE ACCESS
WR
DATA
(IN)
tSADRI
tDACKAD
tHADRI
tACKTR
tSDDATO
tSRWLI
tHRWLI
tRWHPI
tDATTR
tSRWLI
tSDATWH
Figure 10. Synchronous Read/Write—Bus Slave
tHRWLI
tHDATWH
tRWHPI
Rev. B | Page 12 of 48

12 Page





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