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AD1380 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1380
Beschreibung Low Cost 16-Bit Sampling ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
AD1380 Datasheet, Funktion
FEATURES
Complete sampling 16-bit ADC with reference and clock
50 kHz throughput
±1/2 LSB nonlinearity
Low noise SHA: 300 μV p-p
32-lead hermetic DIP
Parallel output
Low power: 900 μW
APPLICATIONS
Medical and analytical instrumentation
Signal processing
Data acquisition systems
Professional audio
Automatic test equipment (ATE)
Telecommunications
GENERAL DESCRIPTION
The AD1380 is a complete, low cost 16-bit analog-to-digital
converter, including internal reference, clock and sample/hold
amplifier. Internal thin-film-on-silicon scaling resistors allow
analog input ranges of ±2.5 V, ±5 V, ±10 V, 0 V to +5 V and
0 V to +10 V.
Important performance characteristics of the AD1380 include
maximum linearity error of ±0.003% of FSR (AD1380KD) and
maximum 16-bit conversion time of 14 μs. Transfer
characteristics of the AD1380 (gain, offset and linearity) are
specified for the combined ADC/sample-and-hold amplifier
(SHA), so total performance is guaranteed as a system. The
AD1380 provides data in parallel with corresponding clock and
status outputs. All digital inputs and outputs are TTL or 5 V
CMOS-compatible.
The serial output function is no longer available after date
code 0120.
Low Cost
16-Bit Sampling ADC
AD1380
FUNCTIONAL BLOCK DIAGRAM
S/H +10V +20V
COMPARATOR GAIN
OUT SPAN SPAN BIPOLAR
IN
ADJ
32 6
7
4
53
AD1380
24 MSB
S/H IN 31
+5V 29
SAMPLE
AND
HOLD
REF
ADC
23 BIT 2
10 BIT 15
DIGITAL 30
COMMON
+15V 2
ANALOG 8
COMMON
TIMING CIRCUITRY
9 LSB
25 NC
27 BUSY
–15V 1
28
START
CONVERT
26
CLOCK
OUT
NC = NO CONNECT
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.






AD1380 Datasheet, Funktion
AD1380
THEORY OF OPERATION
A 16-bit ADC partitions the range of analog inputs into 216
discrete ranges or quanta. All analog values within a given
quantum are represented by the same digital code, usually
assigned to the nominal midrange value. There is an inherent
quantization uncertainty of ±1/2 LSB associated with the
resolution, in addition to the actual conversion errors.
The actual conversion errors associated with ADCs are
combinations of analog errors due to the linear circuitry,
matching and tracking properties of the ladder and scaling
networks, reference error, and power supply rejection. The
matching and tracking errors in the converter have been
minimized by the use of monolithic DACs that include the
scaling network.
The initial gain and offset errors are specified at ±0.1% FSR for
gain and ±0.05% FSR for offset. These errors may be trimmed
to zero by the use of external trim circuits as shown in Figure 3
and Figure 4. Linearity error is defined for unipolar ranges as
the deviation from a true straight line transfer characteristic
from a zero voltage analog input, which calls for a zero digital
output, to a point that is defined as full scale. The linearity error
is based on the DAC resistor ratios. It is unadjustable and is the
most meaningful indication of ADC accuracy. Differential
nonlinearity is a measure of the deviation in the staircase step
width between codes from the ideal least significant bit step size
(Figure 2).
Monotonic behavior requires that the differential linearity error
be less than 1 LSB. However, a monotonic converter can have
missing codes. The AD1380 is specified as having no missing
codes over temperature ranges noted in the Specifications
section.
There are three types of drift error over temperature: offset, gain
and linearity. Offset drift causes a shift of the transfer
characteristic left or right on the diagram over the operating
temperature range. Gain drift causes a rotation of the transfer
characteristic about the zero for unipolar ranges or the minus
full-scale point for bipolar ranges. The worst-case accuracy drift
is the summation of all three drift errors over temperature.
Statistically, however, the drift error behaves as the root-sum-
squared (RSS) and can be shown as
RSS = ∈G 2 + ∈O 2 + ∈L 2
where:
G = gain drift error (ppm / °C).
O = offset drift error (ppm of FSR / °C).
L = linearity error (ppm of FSR / °C).
000 ... 000
ALL BITS ON
GAIN
ERROR
011 ... 111
–1/2LSB
OFFSET
ERROR
+1/2LSB
111 ... 111
ALL BITS OFF
–FSR
2
0
ANALOG INPUT
+FSR
2
–1LSB
Figure 2. Transfer Characteristics for an Ideal Bipolar ADC
Rev. D | Page 6 of 12

6 Page









AD1380 pdf, datenblatt
AD1380
OUTLINE DIMENSIONS
32
1.728 (43.89) MAX
17
1.102 (27.99)
1.079 (27.41)
1 16
0.225 (5.72)
MAX
PIN 1
INDICATOR
(NOTE 1)
0.025 (0.64)
0.015 (0.38)
0.192 (4.88)
0.152 (3.86)
0.025 (0.64)
MIN 0.100 (2.54)
BSC
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.206 (5.23)
0.186 (4.72)
0.120 (3.05)
MAX
0.910 (23.11)
0.890 (22.61)
NOTES:
1. INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE
IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE.
2. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 15. 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H]
(DH-32E)
Dimensions shown in inches and (millimeters)
0.015 (0.38)
0.008 (0.20)
ORDERING GUIDE
Model
Max Linearity Error
AD1380JD
0.006% FSR
AD1380KD
0.003% FSR
Temperature Range
0°C to 70°C
0°C to 70°C
Package Option
Ceramic (DH-32E)
Ceramic (DH-32E)
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00764–0–6/05(D)
Rev. D | Page 12 of 12

12 Page





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