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AD10677 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD10677
Beschreibung 65 MSPS A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD10677 Datasheet, Funktion
FEATURES
65 MSPS sample rate
80 dBFS signal-to-noise ratio
Transformer-coupled analog input
Single PECL clock source
Digital outputs
True binary format
3.3 V and 5 V CMOS-compatible
APPLICATIONS
Low signature radar
Medical imaging
Communications instrumentation
Instrumentation
Antenna array processing
GENERAL DESCRIPTION
The AD10677 is a 16-bit, high performance, analog-to-digital
converter (ADC) for applications that demand increased SNR
levels. Exceptional noise performance and a typical signal-to-
noise ratio of 80 dBFS are obtained by digitally postprocessing
the outputs of four ADCs. A single analog input and PECL
sampling clock and 3.3 V and 5 V power supplies are required.
The AD10677 is assembled using a 0.062-inch laminate board
with three sets of connector interface pads to accommodate
analog and digital isolation. Analog Devices recommends
using the FSI-110-03-G-D-AD-K-TR connector from Samtec.
The overall card fits a 2.2 inch × 2.8 inch PCB specified from
0°C to 70°C.
16-Bit, 65 MSPS A/D Converter
AD10677
FUNCTIONAL BLOCK DIAGRAM
AIN
AIN
ANALOG
POWER
AGND
+5VA
+3.3VE
AGND
AD10677
ADC
ADC
ADC
ADC
14
DOUT0
14
DIGITAL
POST-
PROCES-
14 SING
DOUT15
14
OUTPUT
DATA
BITS
CLOCK
DISTRIBUTION CIRCUIT
DGND +3.3V DGND
ENCODE ENCODE
DIGITAL POWER
Figure 1.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 65 MSPS.
2. Input signal conditioning with optimized noise
performance.
3. Fully tested and guaranteed performance.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD10677 Datasheet, Funktion
AD10677
TEST CIRCUITS
t0
N
N+1 N+2
N+3 N+4
N+5 N+6
ANALOG INPUT
ENCODE, ENCODE
tENC
N
DATA BITS, D[15:0]
tENCL tENCH
N+1
N–9
N+2
tPDH
N–8
N+3
tPDL
N–7
N+4
N–6
N+5 N+6
N–5 N–4
AIN
200Ω
AIN
1:1
Figure 2. Timing Diagram
VCH AVCC
25Ω
500Ω
25Ω
×4
500Ω
VCL
VCH AVCC
500Ω
BUF
T/H
BUF
VREF
BUF
T/H
VCL
Figure 3. Analog Input Stage
ENC
100Ω
ENC
EVCC
37.5kΩ
PECL
DRIVER
Figure 4. Equivalent Encode Input
VDD
MACROCELL
LOGIC
VDD
P
120Ω
N
D0–D15
Figure 5. Digital Output Stage
Rev. D | Page 6 of 20

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AD10677 pdf, datenblatt
AD10677
THEORY OF OPERATION
The AD10677 uses four parallel high speed ADCs in a
correlation technique to improve the dynamic range of the
ADCs. The technique sums the parallel outputs of the four
converters to reduce the uncorrelated noise introduced by the
individual converters. Signals processed through the high speed
adder are correlated and summed coherently. Noise is not
correlated and sums on an rms basis.
The four high speed ADCs use a three-stage subrange architec-
ture. The AD10677 provides complementary analog input pins,
AIN and AIN. Each analog input is centered around 2.4 V and
should swing ±0.55 V around the reference. Because AIN and
AIN are 180 degrees out of phase, the differential analog input
signal is 2.15 V p-p.
The analog input meets a 50 Ω input impedance for easy
interface to commercial cables, filters, drivers, and so on.
The AD10677 encode inputs are ac-coupled to a PECL
differential receiver/driver. The output of the receiver/driver
provides a clock source for a 1:5 PECL clock driver and a
PECL-to-TTL translator. The 1:5 PECL clock driver provides
the differential encode signal for each of the four high speed
ADCs. The PECL-to-TTL translator provides a clock source for
the complex programmable logic device (CPLD).
The digital outputs from the four ADCs drive 120 Ω series
output terminators and are applied to the CPLD for post-
processing. The digital outputs are added together in the
complex programmable logic device through a ripple-carry
adder, which provides the 16-bit data output. The AD10677
provides valid data following nine pipeline delays. The result
is a 16-bit parallel digital CMOS-compatible word coded as
true binary.
THERMAL CONSIDERATIONS
Due to the high power nature of the part, it is critical that the
following thermal conditions be met for the part to perform to
data sheet specifications. This also ensures that the maximum
junction temperature (150°C) is not exceeded.
Operation temperature (TA) must be within 0°C to 70°C.
All mounting standoffs should be fastened to the interface
PCB assembly with 2-56 nuts. This ensures good thermal
paths as well as excellent ground points.
The unit rises to ~72°C (TC) on the heat sink in still air
(0 linear feet per minute (LFM)). The minimum recom-
mended air flow is 100 linear feet per minute (LFM) in
either direction across the heat sink (see Figure 18).
75
70
65
60
55
50
45
40
35
30
0 50 100 150 200 250 300
AIR FLOW (AMBIENT) (LFM)
Figure 18. Temperature (Case) vs. Air Flow (Ambient)
INPUT STAGE
The user is provided with a single-to-differential transformer-
coupled input. The input impedance is 50 Ω and requires a
2.15 V p-p input level to achieve full scale.
ENCODING THE AD10677
The AD10677 encode signal must be a high quality, low phase
noise source to prevent performance degradation. The clock
input must be treated as an analog input signal because aperture
jitter can affect dynamic performance. For optimum perform-
ance, the AD10677 must be clocked differentially.
OUTPUT LOADING
Take care when designing the data receivers for the AD10677.
The complex programmable logic device’s 16-bit outputs drive
120 Ω series resistors to limit the amount of current that can
flow into the output stage. To minimize capacitive loading,
there should be only one gate on each of the output pins. A
typical CMOS gate combined with the PCB trace has a load of
approximately 10 pF. Note that extra capacitive loading
increases output timing and invalidates timing specifications.
Digital output timing is guaranteed with 10 pF.
ANALOG AND DIGITAL POWER SUPPLIES
Care must be taken when selecting a power source. Linear
supplies are recommended. Switching supplies tend to have
radiated components that can be coupled into the ADCs. The
AD10677 features separate analog and digital supply and
ground currents, helping to minimize digital corruption of
sensitive analog signals.
The +3.3VE supply provides power to the clock distribution
circuit. The +3.3VD supply provides power to the digital output
section of the ADCs, the PECL-to-TTL translator, and the
CPLD. Separate +3.3VE and +3.3VD supplies are used to
prevent modulation of the clock signal with digital noise.
Rev. D | Page 12 of 20

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