Datenblatt-pdf.com


AD10200 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD10200
Beschreibung 12-Bit 105 MSPS IF Sampling A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD10200 Datasheet, Funktion
a
Dual Channel, 12-Bit 105 MSPS IF Sampling
A/D Converter with Analog Input
Signal Conditioning
FEATURES
Dual, 105 MSPS Minimum Sample Rate
Channel-Channel Isolation, >80 dB
AC-Coupled Signal Conditioning Included
Gain Flatness up to Nyquist: < 0.2 dB
Input VSWR 1.1:1 to Nyquist
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
0.850 W per Channel
Industrial and Military Grade
APPLICATIONS
Radar IF Receivers
Phased Array Receivers
Communications Receivers
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers
PRODUCT DESCRIPTION
The AD10200 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
AD10200
includes two wide-dynamic range ADCs. Each ADC has a
transformer coupled front-end optimized for Direct-IF sampling.
The AD10200 has on-chip track-and-hold circuitry, and utilizes
an innovative architecture to achieve 12-bit, 105 MSPS perfor-
mance. The AD10200 uses innovative high-density circuit
design to achieve exceptional matching and performance while
still maintaining excellent isolation, and providing for significant
board area savings.
The AD10200 operates with 5.0 V supply for the analog-to-
digital conversion. Each channel is completely independent
allowing operation with independent encode and analog inputs.
The AD10200 is packaged in a 68-lead ceramic chip carrier
package. Manufacturing is done on Analog Devices, Inc. MIL-
38534 Qualified Manufacturers Line (QML) and components
are available up to Class-H (–50°C to +125°C).
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 105 MSPS.
2. Input signal conditioning with full power bandwidth to
250 MHz.
3. Fully tested/characterized performance at 121 MHz AIN.
4. Optimized for IF sampling.
FUNCTIONAL BLOCK DIAGRAM
AINA2
7
AINB2
63
D00A 34
(LSB)
D01A 33
D02A 32
D03A 31
D04A 30
D05A 29
D06A 28
D07A 25
D08A 24
D09A 23
D10A 22
D11A 21
(MSB)
T1A
50
T/H
T1B
AD10200
50
T/H
ADC
12 12
OUTPUT RESISTORS
TIMING
REF
ADC
12
12
OUTPUT RESISTORS
REF
TIMING
50 D00B
(LSB)
49 D01B
48 D02B
47 D03B
46 D04B
45 D05B
42 D06B
41 D07B
40 D08B
39 D09B
38 D10B
37 D11B
(MSB)
18 17
3
ENCODEA ENCODEA REF_A_OUT
56
REF_B_OUT
53 54
ENCODEB ENCODEB
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
©Analog Devices, Inc., 2001–2016






AD10200 Datasheet, Funktion
PIN CONFIGURATION
AD10200
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
AGNDA 10
AGNDA 11
DNC 12
AGNDA 13
AVCC 14
DNC 15
AGNDA 16
ENCODEA 17
ENCODEA 18
AGNDA 19
DVCC 20
(MSB) D11A 21
D10A 22
D9A 23
D8A 24
D7A 25
DGNDA 26
PIN 1
IDENTIFIER
AD10200
TOP VIEW
(Not to Scale)
60 AGNDB
59 AGNDB
58 DNC
57 DNC
56 REF_B_OUT
55 AGNDB
54 ENCODEB
53 ENCODEB
52 AGNDB
51 DVCC
50 D0B (LSB)
49 D1B
48 D2B
47 D3B
46 D4B
45 D5B
44 DGNDB
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC = NO CONNECT
Pin No.
1
2, 5, 9–11, 13, 16, 19, 35
3
6, 62
7
4, 8, 12, 15, 57, 58, 64, 67
14, 66
17
18
20
21–25, 28–34
26, 27
36, 52, 55, 59–61, 65, 68
37–42, 45–50
43, 44
51
53
54
56
63
PIN FUNCTION DESCRIPTIONS
Mnemonic
SHIELD
AGNDA
VREF_A_OUT
NC
AINA2
DNC
AVCC
ENCODEA
ENCODEA
DVCC
D11A–D7A,
D6A–D0A
DGNDA
AGNDB
D11B–D6B,
D5B–D0B
DGNDB
DVCC
ENCODEB
ENCODEB
VREF_B_OUT
AINB2
Function
Internal Ground Shield between Channels
A Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
A Channel Internal Voltage Reference
No Connection
Analog Input for A Side ADC
Do Not Connect
Analog Positive Supply Voltage (Nominally 5.0 V)
Complement of Encode
Data conversion initiated on the rising edge of ENCODE input.
Digital Positive Supply Voltage (Nominally 3.3 V)
Digital Outputs for ADC A. D0 (LSB)
A Channel Digital Ground
B Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
Digital Outputs for ADC B. D0 (LSB)
B Channel Digital Ground
Digital Positive Supply Voltage (Nominally 3.3 V)
Data conversion initiated on rising edge of ENCODE input.
Complement of Encode
B Channel Internal Voltage Reference
Analog Input for B Side ADC
REV. B
–5–

6 Page









AD10200 pdf, datenblatt
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 8) represents
a typical implementation of the AD10200. The pinout of the
AD10200 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high-slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.
AD10200
EVALUATION BOARD
The AD10200 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD10200
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10200. The board requires an analog input signal, encode
clock and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD10200. The digital outputs of the
AD10200 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
Figure 8. Evaluation Board Mechanical Layout
REV. B
–11–

12 Page





SeitenGesamt 20 Seiten
PDF Download[ AD10200 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD1020(AD1xxx) Hybrid ICNichicon
Nichicon
AD1020012-Bit 105 MSPS IF Sampling A/D ConverterAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche