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ACX301AKM Schematic ( PDF Datasheet ) - Sony Corporation

Teilenummer ACX301AKM
Beschreibung 5.1cm (2.0 Type) NTSC/PAL Color LCD Panel (Module with Backlight)
Hersteller Sony Corporation
Logo Sony Corporation Logo 




Gesamt 26 Seiten
ACX301AKM Datasheet, Funktion
ACX301AKM
5.1cm (2.0 Type) NTSC/PAL Color LCD Panel (Module with Backlight)
Description
The ACX301AKM is an LCD panel module with
back light developed exclusively for the ACX301AK
5.1cm diagonal active matrix TFT-LCD panel
addressed by low temperature polycrystalline silicon
transistors with built-in peripheral driving circuitry.
This module provides full-color representation for
NTSC and PAL systems. In addition, RGB dots are
arranged in a delta pattern that provides smooth
picture quality without fixed color patterns compared
to vertical stripe and mosaic patterns.
Features
Number of active dots: 200,000, 5.1cm (2.0 Type) in diagonal
Horizontal resolution: 440 TV lines
Center luminance: 250cd/m2 (typ.)
High contrast ratio with normally white mode: 200 (typ.)
Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
Low voltage, low power consumption: 12V drive: 50mW (panel block, typ.)
0.48W (CCFLpower consumption, typ.)
Cold cathode fluorecene lamp
Smooth pictures with a RGB delta arrangement
Supports NTSC/PAL
Built-in picture quality improvement circuit
Up/down and/or right/left inverse display function
16:9 screen display function
LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
Dirt-resistant surface treatment
Thin package using a dedicated backlight (5.8mm thick)
High color reproductivity using a backlight optimum for LCD panels
Element Structure
Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline
silicon transistors
Edge-light type backlight using cold cathode tubes
Number of pixels
Total number of dots:
896 (H) × 230 (V) = 206,080
Number of active dots:
880 (H) × 228 (V) = 200,640
Module dimensions
Package dimensions:
50.5 (W) × 45.6 (D) × 5.8 (H) (mm)
Effective display dimensions: 40.5 (H) × 30.6 (V) (mm)
Applications
LCD monitors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99633A01-PS






ACX301AKM Datasheet, Funktion
ACX301AKM
Input Equivalent Circuits of Panel Block
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal input pins. All pins are connected to VSS with a
high resistance of 1M(typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) RED, GREEN, BLUE, PSIG
HVDD
Input
1M
(2) HCK1, HCK2
HVDD
HCK1
HCK2
(3) HST, WIDE, REF
Input
REF
HVDD
350
(4) RGT, REF
Input
REF
HVDD
2k
(5) VST, VCK, EN, REF
Input
REF
VVDD
800
1M
350
1M
2k
1M
Signal line
HVDD
H level shifter and
shift register circuit
1M
HVDD
Level conversion
circuit
1M
HVDD
Level conversion
circuit
1M
VVDD
800
1M
6
Level conversion
circuit
1M

6 Page









ACX301AKM pdf, datenblatt
<Vertical Shift Register Driving Waveforms>
Item Symbol
Waveform
VST rise time
VST fall time
VST
VST data setup time
trVst
tfVst
tdVst
VST
10%
90%
6
VST
trVst
50%
50%
90%
10%
tfVst
50%
50%
VST data hold time
thVst
VCK
tdVst
thVst
VCK rise time
VCK
VCK fall time
trVck
90%
VCK
10%
90%
10%
tfVck
trVck tfVck
EN rise time
EN fall time
EN EN fall to VCK rise/fall
time
EN pulse width
WIDE rise time
WIDE fall time
trEn
tfEn
tdEn
90%
90%
10% 10%
EN
6
VCK
tfEn trEn
50%
twEn
EN
50%
50%
twEn
tdEn
trWide
tfWide
WIDE
90%
10%
trWide
90%
10%
tfWide
ACX301AKM
Conditions
VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = 32µs
VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
8 WIDE pulse width
WIDE
WIDE fall to EN rise time
twvWide WIDE
tov1Wide
6
WIDE
50%
twvWide
50%
50%
EN fall to WIDE fall time tov2Wide
EN
50%
50%
tov1Wide
tov2Wide
8 WIDE represents 1F cycle as shown in the Vertical Timing.
12

12 Page





SeitenGesamt 26 Seiten
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