ACTS00K Datasheet PDF - Intersil Corporation
| Part Number | ACTS00K | |
| Description | Radiation Hardened Quad 2-Input NAND Gate | |
| Manufacturers | Intersil Corporation | |
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There is a preview and ACTS00K download ( pdf file ) link at the bottom of this page. Total 8 Pages | ||
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ACTS00MS
April 1995
Radiation Hardened
Quad 2-Input NAND Gate
Features
Pinouts
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C
TOP VIEW
• Single Event Upset (SEU) Immunity
<1 x 10-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm2/mg
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2V Min
• Input Current ≤1µA at VOL, VOH
Description
The Intersil ACTS00MS is a radiation hardened quad 2-Input NAND
gate. A high logic level on both inputs forces the output to a logic low
state.
The ACTS00MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
14 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
B4
A4
Y4
B3
A3
Y3
Ordering Information
PART NUMBER
ACTS00DMSR
ACTS00KMSR
ACTS00D/Sample
ACTS00K/Sample
ACTS00HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
Truth Table
INPUTS
OUTPUT
An Bn Yn
L LH
L HH
HLH
HH L
NOTE: L = Logic Level Low, H = Logic Level High
Functional Diagram
An
Bn
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Yn
Spec Number 518822
File Number 3564.1
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Specifications ACTS00MS
Intersil - Space Products MS Screening
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM)
Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull Method 2023
100% Internal Visual Inspection Method 2010
100% Temperature Cycling Method 1010 Condition C
(-65o to +150oC)
100% Constant Acceleration
100% PIND Testing
100% External Visual Inspection
100% Serialization
100% Initial Electrical Test
100% Static Burn-In 1 Method 1015, 24 Hours at +125oC Min
100% Interim Electrical Test 1 (Note 1)
100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min
100% Interim Electrical Test 2 (Note 1)
100% Dynamic Burn-In Method 1015, 240 Hours at +125oC
or 180 Hours at +135oC
100% Interim Electrical Test 3 (Note 1)
100% Final Electrical Test
100% Fine and Gross Seal Method 1014
100% Radiographics Method 2012 (2 Views)
100% External Visual Method 2009
Group A (All Tests) Method 5005 (Class S)
Group B (Optional) Method 5005 (Class S) (Note 2)
Group D (Optional) Method 5005 (Class S) (Note 2)
CSI and/or GSI (Optional) (Note 2)
Data Package Generation (Note 3)
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com-
bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
Propagation Delay Timing Diagram and Load Circuit
VIH
VSS
VOH
VOL
VS INPUT
TPLH
VS
TPHL
OUTPUT
DUT
CL
50pF
TEST
POINT
RL
500Ω
AC VOLTAGE LEVELS
PARAMETER
ACTS
VCC
4.50
VIH 3.00
VS 1.30
VIL 0
GND
0
UNITS
V
V
V
V
V
Spec Number 518822
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ACTS00K electronic component. |
| Information | Total 8 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ACTS00K.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| ACTS00D | The function is Radiation Hardened Quad 2-Input NAND Gate. Intersil Corporation | |
| ACTS00DMSR | The function is Radiation Hardened Quad 2-Input NAND Gate. Intersil Corporation | |
| ACTS00HMSR | The function is Radiation Hardened Quad 2-Input NAND Gate. Intersil Corporation | |
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