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AD5554 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5554
Beschreibung Quad/ Current-Output Serial-Input/ 16-Bit/14-Bit DACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD5554 Datasheet, Funktion
a
Quad, Current-Output
Serial-Input, 16-Bit/14-Bit DACs
AD5544/AD5554
FEATURES
AD5544 16-Bit Resolution
AD5554 14-Bit Resolution
2 mA Full-Scale Current ؎20%, with VREF = ؎10 V
2 s Settling Time
VSS BIAS for Zero-Scale Error Reduction @ Temp
Midscale or Zero-Scale Reset
Four Separate 4Q Multiplying Reference Inputs
SPI-Compatible 3-Wire Interface
Double Buffered Registers Enable
Simultaneous Multichannel Change
Internal Power ON Reset
Compact SSOP-28 Package
APPLICATIONS
Automatic Test Equipment
Instrumentation
Digitally-Controlled Calibration
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current-output, digital-
to-analog converters are designed to operate from a single 5 V
supply.
The applied external reference input voltage (VREF) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI- and microcontroller-compatible inputs using
serial-data-in (SDI), clock (CLK), and a chip-select (CS). In
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common level-sensitive
load-DAC strobe (LDAC) input allows simultaneous update of
all DAC outputs from previously loaded input registers. Addi-
tionally, an internal power ON reset forces the output voltage to
zero at system turn ON. An MSB pin allows system reset asser-
tion (RS) to force all registers to zero code when MSB = 0, or
to half-scale code when MSB = 1.
AD5544/AD5554 are packaged in the compact SSOP-28.
SDO
SDI
CS
CLK
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 16
D10
D11
D12
D13
D14
D15
A0
A1
EN
DAC A
B
C
D
2:4
DECODE
DGND
INPUT
REGISTER R
INPUT
REGISTER R
INPUT
REGISTER R
INPUT
REGISTER R
POWER-
ON
RESET
RS MSB
VREF A B C D
DAC A
REGISTER R
DAC A
DAC B
REGISTER R
DAC B
DAC C
REGISTER R
DAC C
DAC D
REGISTER R
DAC D
AD5544
LDAC
VSS
VDD
RFBA
IOUTA
AGNDA
RFBB
IOUTB
AGNDB
RFBC
IOUTC
AGNDC
RFBD
IOUTD
AGNDD
AGNDF
1.0
0.5
0.0
–0.5
–1.0
1.0
0.5
0.0
–0.5
–1.0
1.0
0.5
0.0
–0.5
–1.0
1.0
0.5
0.0
–0.5
–1.0
0
DAC A
DAC B
DAC C
DAC D
8192 16384 24576 32768 40960 49152 57344 65536
CODE – Decimal
Figure 1. AD5544 INL vs. Code Plot (TA = 25°C)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD5554 Datasheet, Funktion
AD5544/AD5554
SDI A1 A0 D15 D14 D13 D12 D11 D10
CLK
CS
LDAC
tCSS
tDS tDH
tCH tCL
tPD
SDO
Figure 2. AD5544 Timing Diagram
D1 D0
INPUT
REG
LD
tCSH
tLDS
tLDAC
tLDH
SDI A1 A0 D13 D12 D11 D10 D09 D08
CLK
CS
LDAC
tCSS
tDS tDH
tCH tCL
tPD
SDO
D1 D0
INPUT
REG
LD
tCSH
tLDS
tLDAC
tLDH
Figure 3. AD5554 Timing Diagram
CS CLK
HX
LL
L +
LH
+ L
HX
HX
HX
HX
HX
LDAC RS
HH
HH
HH
HH
HH
LH
HH
+ H
HL
HL
Table I. AD5544 Control-Logic Truth Table
MSB
X
X
X
X
X
X
X
X
0
H
Serial Shift Register Function
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Input Register Function DAC Register
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Selected DAC Updated Latched
with Current SR Contents
Latched
Transparent
Latched
Latched
Latched
Latched
Latched Data = 0000H
Latched Data = 8000H
Latched Data = 0000H
Latched Data = 8000H
–6– REV. 0

6 Page









AD5554 pdf, datenblatt
AD5544/AD5554
100
VDD = 5V ؎10%
90 TA = 25؇C
80
70
60
50
40
30
20
100
1k 10k 100k
CLOCK FREQUENCY Hz
1M
TPC 17. AD5544/AD5554 Power Supply Rejection
vs. Frequency
55
54
VDD = 5V
VREF = 10V
53 LOGIC = VDD
52
51
50
49
48
47
46
50 25 0 25 50 75 100 125 150
TEMPERATURE ؇C
TPC 18. AD5544/AD5554 Power Supply Current
vs. Temperature
600
VDD = 5V
500
VREF = 10V
TA = 25؇C
400
300
200
100
0
012345
LOGIC INPUT VOLTAGE Volts
TPC 19. AD5544/AD5554 Power Supply Current
vs. Logic Input Voltage
CIRCUIT OPERATION
The AD5544 and AD5554 contain four, 16-bit and 14-bit,
current-output, digital-to-analog converters respectively. Each
DAC has its own independent multiplying reference input. Both
AD5544/AD5554 use 3-wire SPI compatible serial data inter-
face, with a configurable asynchronous RS pin for half-scale
(MSB = 1) or zero-scale (MSB = 0) preset. In addition, an
LDAC strobe enables four channel simultaneous updates for
hardware synchronized output voltage changes.
D/A Converter Section
Each part contains four current-steering R-2R ladder DACs.
Figure 4 shows a typical equivalent DAC. Each DAC contains
a matching feedback resistor for use with an external I-to-V
converter amplifier. The RFBX pin is connected to the output of
the external amplifier. The IOUTX terminal is connected to the
inverting input of the external amplifier. The AGNDX pin should
be Kelvin-connected to the load point in the circuit requiring
the full 16-bit accuracy. These DACs are designed to operate
with both negative or positive reference voltages. The VDD power
pin is only used by the logic to drive the DAC switches ON and
OFF. Note that a matching switch is used in series with the
internal 5 kfeedback resistor. If users are attempting to mea-
sure the value of RFB, power must be applied to VDD in order to
achieve continuity. An additional VSS bias pin is used to guard
the substrate during high temperature applications to minimize
zero-scale leakage currents that double every 10°C. The DAC
output voltage is determined by VREF and the digital data (D) as:
VOUT = −VREF × D (For AD5544)
65536
(Equation 1)
VOUT = −VREF × D (For AD5554)
16384
(Equation 2)
Note that the output polarity is opposite to the VREF polarity for
dc reference voltages.
–12–
REV. 0

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