Datenblatt-pdf.com


AD5533 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5533
Beschreibung 32-Channel Infinite Sample-and-Hold
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD5533 Datasheet, Funktion
a
32-Channel Infinite
Sample-and-Hold
AD5533*
FEATURES
Infinite Sample-and-Hold Capability to ؎0.018% Accuracy
High Integration: 32-Channel SHA in 12 ؋ 12 mm2 LFBGA
Per Channel Acquisition Time of 16 s max
Adjustable Voltage Output Range
Output Voltage Span 10 V
Output Impedance 0.5
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Parallel Interface
Temperature Range –40؇C to +85؇C
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O
GENERAL DESCRIPTION
The AD5533 combines a 32-channel voltage translation function
with an infinite output hold capability. An analog input voltage
on the common input pin, VIN, is sampled and its digital repre-
sentation transferred to a chosen DAC register. VOUT for this
DAC is then updated to reflect the new contents of the DAC
register. Channel selection is accomplished via the parallel address
inputs A0–A4 or via the serial input port. The output voltage
range is determined by the offset voltage at the OFFS_IN pin
and the gain of the output amplifier. It is restricted to a range
from VSS + 2 V to VDD – 2 V because of the headroom of the
output amplifier.
The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V to
5.25 V, VSS = –4.75 V to –16.5 V and VDD = 8 V to 16.5 V and
requires a stable 3 V reference on REF_IN as well as an offset
voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. Infinite Droopless Sample-and-Hold Capability.
2. The AD5533 is available in a 74-lead LFBGA package with a
body size of 12 mm × 12 mm.
FUNCTIONAL BLOCK DIAGRAM
DVCC AVCC REF IN REF OUT OFFS IN VDD VSS
VIN
TRACK / RESET
BUSY
DAC GND
AGND
DGND
SER / PAR
ADC
DAC
VOUT 0
AD5533
INTERFACE
CONTROL
LOGIC
SCLK DIN DOUT
DAC
DAC
VOUT 31
OFFS OUT
ADDRESS INPUT REGISTER
WR
SYNC/ CS A4 –A0 CAL OFFSET SEL
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD5533 Datasheet, Funktion
AD5533
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V
VIN to AGND, DAC_GND . . . . . . . . . . . . . . . –0.3 V to +7 V
VOUT0–31 to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
VOUT0–31 toVSS . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +24 V
OFFS_IN to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
OFFS_OUT to AGND . . . . AGND – 0.3 V to AVCC + 0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead LFBGA Package, θJA Thermal Impedance . . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
Model
AD5533ABC-1
AD5532ABC-1*
AD5532ABC-2*
AD5532ABC-3*
AD5532ABC-5*
EVAL-AD5532EB
*Separate Data Sheet.
ORDERING GUIDE
Function
32-Channel SHA Only
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
32 DACs, 32-Channel SHA
AD5532/AD5533 Evaluation Board
Output
Impedance
0.5 typ
0.5 typ
0.5 typ
500 typ
1 ktyp
Output
Voltage Span
10 V
10 V
20 V
10 V
10 V
Package
Description
74-Lead LFBGA
74-Lead LFBGA
74-Lead LFBGA
74-Lead LFBGA
74-Lead LFBGA
Package
Option
BC-74
BC-74
BC-74
BC-74
BC-74
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5533 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6– REV. 0

6 Page









AD5533 pdf, datenblatt
AD5533
Reset Function
The reset function on the AD5533 can be used to reset all nodes
on this device to their power-on-reset condition. This is imple-
mented by applying a low-going pulse of between 50 ns and 150 ns
to the TRACK/RESET pin on the device. If the applied pulse
is less than 50 ns it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 150 ns this pin adopts
its track function on the selected channel, VIN is switched to the
output buffer and an acquisition on the channel will not occur
until a rising edge of TRACK.
TRACK Function
Normally in SHA mode of operation, TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, VIN is switched
to the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK. At this stage the BUSY pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
VIN is free to change again without affecting this output value.
This is useful in an application where the user wants to ramp up
VIN until VOUT reaches a particular level (Figure 12). VIN does
not need to be acquired continuously while it is ramping up.
TRACK can be kept low and only when VOUT has reached its
desired voltage is TRACK brought high. At this stage, the
acquisition of VIN begins.
In the example shown, a desired voltage is required on the out-
put of the pin driver. This voltage is represented by one input to
a comparator. The microcontroller/microprocessor ramps up
the input voltage on VIN through a DAC. TRACK is kept low
while the voltage on VIN ramps up so that VIN is not continu-
ally acquired. When the desired voltage is reached on the output of
the pin driver, the comparator output switches. The µC/µP then
knows what code is required to be input in order to obtain the
desired voltage at the DUT. The TRACK input is now brought
high and the part begins to acquire VIN. BUSY goes low until VIN
has been acquired. When BUSY goes high, the output buffer
is switched from VIN to the output of the DAC.
MODES OF OPERATION
The AD5533 can be used in three different modes. These modes
are set by two mode bits, the first two bits in the serial word.
The 01 option (DAC Mode) is not available for the AD5533.
To avail of this mode refer to the AD5532 data sheet. If you
attempt to set up DAC mode, the AD5533 will enter a test-mode
and a 24-clock write will be necessary to clear this.
Mode Bit 1
0
0
1
1
Table II. Modes of Operation
Mode Bit 2
0
1
0
1
Operating Mode
SHA Mode
DAC Mode (Not Available)
Acquire and Readback
Readback
1. SHA Mode
In this standard mode a channel is addressed and that channel
acquires the voltage on VIN. This mode requires a 10-bit write
to address the relevant channel (VOUT0–VOUT31, offset channel
or all channels). MSB is written first.
2. Acquire and Readback Mode
This mode allows the user to acquire VIN and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and VIN is acquired in 16 µs (max).
Following the acquisition, after the next falling edge of SYNC
the data in the relevant DAC register is clocked out onto the
DOUT line in a 14-bit serial format. During readback DIN is
ignored. The full acquisition time must elapse before the DAC
register data can be clocked out.
3. Readback Mode
Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the DOUT line in a 14-bit serial format.
The user must allow 400 ns (min) between the last SCLK fall-
ing edge in the 10-bit write and the falling edge of SYNC in
the 14-bit readback. The serial write and read words can be seen in
Figure 13.
This feature allows the user to read back the DAC register code
of any of the channels. Readback is useful if the system has been
calibrated and the user wants to know what code in the DAC
corresponds to a desired voltage on VOUT.
INTERFACES
SERIAL INTERFACE
The SER/PAR pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:
SYNC, DIN, SCLK
Standard 3-wire interface pins. The SYNC pin is shared
with the CS function of the parallel interface.
DOUT
Data Out pin for reading back the contents of the DAC regis-
ters. The data is clocked out on the rising edge of SCLK and
is valid on the falling edge of SCLK.
Cal Bit
When this is high all 32 channels acquire VIN simultaneously.
The acquisition time is then 45 µs (typ) and accuracy may be
reduced.
Offset_Sel Bit
If this bit is set high, the offset channel is selected and Bits
A4–A0 are ignored.
Test Bit
This must be set low for correct operation of the part.
A4–A0
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
–12–
REV. 0

12 Page





SeitenGesamt 16 Seiten
PDF Download[ AD5533 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD5530Serial Input/ Voltage Output 12-/14-Bit DACsAnalog Devices
Analog Devices
AD5531Serial Input/ Voltage Output 12-/14-Bit DACsAnalog Devices
Analog Devices
AD553232-Channel/ 14-Bit Voltage-Output DACAnalog Devices
Analog Devices
AD5532B14-Bit DACAnalog Devices
Analog Devices
AD5532HS32-Channel 14-Bit DAC with High-Speed 3-Wire Serial InterfaceAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche