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PDF AD5516 Data sheet ( Hoja de datos )
| Número de pieza | AD5516 | |
| Descripción | 16-Channel/ 12-Bit Voltage-Output DAC with 14-Bit Increment Mode | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a 16-Channel, 12-Bit Voltage-Output DAC
with 14-Bit Increment Mode
AD5516*
FEATURES
High Integration:
16-Channel DAC in 12 mm ؋ 12 mm LFBGA
14-Bit Resolution via Increment/Decrement Mode
Guaranteed Monotonic
Low Power, SPITM, QSPITM, MICROWIRETM, and DSP-
Compatible
3-Wire Serial Interface
Output Impedance 0.5 ⍀
Output Voltage Range
؎2.5 V (AD5516-1)
؎5 V (AD5516-2)
؎10 V (AD5516-3)
Asynchronous Reset-Facility (via RESET Pin)
Asynchronous Power-Down Facility (via PD Pin)
Daisy-Chain Mode
Temperature Range: –40؇C to +85؇C
GENERAL DESCRIPTION
The AD5516 is a 16-channel, 12-bit voltage-output DAC. The
selected DAC register is written to via the 3-wire serial interface.
DAC selection is accomplished via address bits A3–A0. 14-bit
resolution can be achieved by fine adjustment in Increment/
Decrement Mode (Mode 2). The serial interface operates at
clock rates up to 20 MHz and is compatible with standard SPI,
MICROWIRE, and DSP interface standards. The output volt-
age range is fixed at ± 2.5 V (AD5516-1), ± 5 V (AD5516-2),
and ± 10 V (AD5516-3). Access to the feedback resistor in each
channel is provided via RFB0 to RFB15 pins.
The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V to
5.25 V, VSS = –4.75 V to –12 V, and VDD = +4.75 V to +12 V
and requires a stable 3 V reference on REF_IN.
PRODUCT HIGHLIGHTS
1. Sixteen 12-bit DACs in one package, guaranteed monotonic
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Optical Networks
Industrial Control Systems
Data Acquisition
Low Cost I/O
2. Available in a 74-lead LFBGA package with a body size of
12 mm ؋ 12 mm
FUNCTIONAL BLOCK DIAGRAM
RESET
BUSY
DACGND
AGND
DGND
DCEN
DVCC
AVCC
AD5516
ANALOG
CALIBRATION
LOOP
MODE1
INTERFACE
CONTROL
LOGIC
REF_IN
VBIAS
VDD
VSS
RO F F S
RFB
DAC
RO F F S
RFB
DAC
RO F F S
RFB
DAC
RO F F S
RFB
MODE2
7-BIT BUS
DAC
POWER-DOWN
LOGIC
RFB0
VOUT0
RFB1
VOUT1
RFB14
VOUT14
RFB15
VOUT15
SCLK DIN DOUT SYNC
*Protected by U.S. Patent No. 5,969,657; other patents pending
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
PD
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DACGND . . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DACGND . . . . . –0.3 V to AVCC + 0.3 V
VOUT 0–15 to AGND . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
RFB 0–15 to AGND . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial . . . . . –40°C to +85°C
AD5516
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ MAX) . . . . . . . . . . . . . . . . . . . 150°C
74-Lead LFBGA Package, JA Thermal Impedance . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
Model
AD5516ABC-1
AD5516ABC-2
AD5516ABC-3
ORDERING GUIDE
Function
16 DACs
16 DACs
16 DACs
Output Voltage Span
± 2.5 V
±5 V
± 10 V
Package Option
74-Lead LFBGA
74-Lead LFBGA
74-Lead LFBGA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5516 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
5 Page 
AD5516
The user must allow 200 ns (min) between two consecutive
Mode 2 writes in standalone mode and 400 ns (min) between
two consecutive Mode 2 writes in daisy-chain mode.
See Figures 4 and 5 for Mode 1 and Mode 2 data formats.
When MODE bits = 11, the device is in No Operation mode.
This may be useful in daisy-chain applications where the user
does not wish to change the settings of the DACs. Simply write
11 to the MODE bits and the following address and data bits
will be ignored.
SERIAL INTERFACE
The AD5516 has a 3-wire interface that is compatible with SPI/
QSPI/MICROWIRE and DSP interface standards. Data is written
to the device in 18-bit words. This 18-bit word consists of two
mode bits, four address bits, and 12 data bits as shown in Figure 4.
The serial interface works with both a continuous and burst
clock. The first falling edge of SYNC resets a counter that counts
the number of serial clocks to ensure the correct number of bits
are shifted in and out of the serial shift registers. Any further
edges on SYNC are ignored until the correct number of bits are
shifted in or out. In order for another serial transfer to take
place, the counter must be reset by the falling edge of SYNC.
A3–A0
Four address bits (A3 = MSB Address, A0 = LSB). These are
used to address one of 16 DACs.
Table II. Selected DAC
A3 A2 A1 A0
00 0 0
00 0 1
:: : :
11 1 1
Selected DAC
DAC 0
DAC 1
DAC 15
DB11–DB0
These are used to write a 12-bit word into the addressed DAC
register. Figures 1 and 2 show the timing diagram for a write
cycle to the AD5516.
SYNC FUNCTION
In both standalone and daisy-chain modes, SYNC is an edge-
triggered input that acts as a frame synchronization signal and
chip enable. Data can only be transferred into the device while
SYNC is low. To start the serial data transfer, SYNC should be
taken low observing the minimum SYNC falling to SCLK falling
edge setup time, t3.
Standalone Mode (DCEN = 0)
After SYNC goes low, serial data will be shifted into the device’s
input shift register on the falling edges of SCLK for 18 clock
pulses. After the falling edge of the 18th SCLK pulse, data will
automatically be transferred from the input shift register to the
addressed DAC.
SYNC must be taken high and low again for further serial data
transfer. SYNC may be taken high after the falling edge of the
18th SCLK pulse, observing the minimum SCLK falling edge
to SYNC rising edge time, t6. If SYNC is taken high before the
18th falling edge of SCLK, the data transfer will be aborted and
the addressed DAC will not be updated. See the timing diagram
in Figure 1.
Daisy-Chain Mode (DCEN = 1)
In daisy-chain mode, the internal gating on SCLK is disabled.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than 18 clock pulses are applied,
the data ripples out of the shift register and appears on the DOUT
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next device in the chain, a multidevice interface is
constructed. Eighteen clock pulses are required for each device
in the system. Therefore, the total number of clock cycles must
equal 18N where N is the total number of devices in the chain.
See the timing diagram in Figure 2.
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents any further data being clocked into the
input shift register. A burst clock containing the exact number of
clock cycles may be used and SYNC taken high some time later.
After the rising edge of SYNC, data is automatically transferred
from each device’s input shift register to the addressed DAC.
RESET Function
The RESET function on the AD5516 can be used to reset all
nodes on this device to their power-on reset condition. This is
implemented by applying a low-going pulse of minimum 20 ns
to the RESET Pin on the device.
Table III. Typical Power-ON Values
Device
AD5516-1
AD5516-2
AD5516-3
Output Voltage
–0.073 V
–0.183 V
–0.391 V
BUSY Output
During conversion, the BUSY output is low and all SCLK
pulses are ignored. At the end of a conversion, BUSY goes high
indicating that the update of the addressed DAC is complete. It
is recommended that SCLK is not pulsed while BUSY is low.
MICROPROCESSOR INTERFACING
The AD5516 is controlled via a versatile 3-wire serial interface
that is compatible with a number of microprocessors and DSPs.
AD5516 to ADSP-2106x SHARC DSP Interface
The ADSP-2106x SHARC DSPs are easily interfaced to the
AD5516 without the need for extra logic.
The AD5516 expects a t3 (SYNC falling edge to SCLK falling
edge setup time) of 15 ns min. Consult the ADSP-2106x User
Manual for information on clock and frame sync frequencies for
the SPORT register and contents of the TDIV, RDIV registers.
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD5516.PDF ] | |
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