PDF AD53500 Data sheet ( Hoja de datos )

Número de pieza	AD53500
Descripción	High Speed/ High Current Capability Pin Driver
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES –2 V to +6 V Output Range 2.5 ⍀ Output Resistance 2.5 ns Tr/Tf for a 3 V Step 300 MHz Toggle Rate Can Drive 25 ⍀ Lines and Lower Peak Dynamic Current Capability of 400 mA Inhibit Leakage <1 ␮A On-Chip Temperature Sensor APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems Instrumentation and Characterization Equipment High Speed, High Current Capability Pin Driver AD53500 FUNCTIONAL BLOCK DIAGRAM VH DATA DATA INH INH VL VCC VCC VEE VEE 39nF 39nF DRIVER 2⍀ VHDCPL VOUT AD53500 1.0␮A/K VLDCPL TVCC THERM GND GND GND GND GND PRODUCT DESCRIPTION: The AD53500 is a complete high speed driver designed for use in digital or mixed signal test systems where high speed and high output drive capabilities are needed. Combining a high speed monolithic process and a unique surface mount package, this product attains superb electrical performance while preserving optimum packing densities and long-term reliability thanks to an ultrasmall 20-lead, PSOP package with built-in heat sink. High and low reference levels can be set within a –2 V to +6 V range with low offset voltage and high gain accuracy. A 2.5 Ω output resistance allows use of an external backmatch resistor for application to 50 Ω, 25 Ω or other complex impedance load requirements. Without a backmatch resistor it is also capable of driving highly capacitive loads, typically achieving a rise/fall time of less than 10 ns with a 1000 pF capacitance. To test I/O devices, the pin driver can be switched into a high impedance state (Inhibit Mode), electrically removing the driver from the path. The pin driver leakage current in inhibit is typically less than 1 µA and output capacitance is typically less than 18 pF. Transitions from HI/LO or to inhibit are controlled through the data and inhibit inputs. The input circuitry utilizes high-speed differential inputs with a common-mode range of –2 V to +5 V. This allows for direct interface to the precision of differential ECL timing or the simplicity of stimulating the pin driver from a single-ended CMOS or TTL logic source or any combination over the common-mode range. The analog logic HI/LO inputs are equally easy to interface, typically requiring 50 µA of bias current. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 1 page AD53500 APPLICATION INFORMATION Power Supply Distribution, Bypassing and Sequencing The AD53500 draws substantial transient currents from its power supplies when switching between states and careful de- sign of the power distribution and bypassing is key to obtaining specified performance. Supplies should be distributed using broad, low inductance traces or (preferably) planes in a multi- layered board with a dedicated ground-plane layer. All of the device’s power supply pins should be used to minimize the inter- nal inductance presented by the part’s bond wires. Each supply must be bypassed to ground with at least one 0.1 µF capacitor; chip-style capacitors are preferable as they minimize inductance. One or more 10 µF (or greater) Tantalum capacitors per board are also advisable to provide additional local energy storage. The AD53500’s current-limit circuitry also requires external bypass capacitors. Figure 2 shows a simplified schematic of the positive current-limit circuit. Excessive collector current in output transistor Q49 creates a voltage drop across the 5 Ω resistor, which turns on PNP transistor Q48. Q48 diverts the rising-edge slew current, shutting down the current mirror and removing the output stage’s base drive. The VHDCPL pin should be bypassed to the positive supply with a 0.039 µF capacitor, while the VLDCPL pin (not shown) requires a similar capacitor to the negative supply. These capacitors ensure that the AD53500 does not current-limit during normal output transitions up its full 8 V rated step size. Both capacitors must have minimum- length connections to the AD53500. Here again, chip capacitors are ideal. Several points about the current-limit circuitry should be noted. First, the limiting currents are not tightly controlled, as they are functions of both absolute transistor VBE and junction tempera- ture; higher dc output current is available at lower junction temperatures. Second, it is essential to connect the VHDCPL capacitor to the positive supply (and the VLDCPL capacitor to the negative supply)—failure to do so causes considerable thermal stress in the current-limiting resistor(s) during normal supply sequencing and may ultimately cause them to fail, rendering the part nonfunctional. Finally, the AD53500 may appear to func- tion normally for small output steps (less than 3 V or so) if one or both of these caps is absent, but it may exhibit excessive rise or fall times for steps of larger amplitude. The AD53500 does not require special power-supply sequenc- ing. However, good design practice dictates that digital and analog control signals not be applied to the part before the sup- plies are stable. Violating this guideline will not normally de- stroy the part, but the active inputs can draw considerable current until the main supplies are applied. 5⍀ Q48 V+ VHDCPL RISING-EDGE SLEW CONTROL CURRENT LEVEL-SHIFTED LOGIC DRIVE VH V– Q49 OUT Q50 Figure 2. Simplified Schematic of the AD53500 Output Stage and Positive Current-Limit Circuitry REV. 0 –5– 5 Page

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