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AD5334 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5334
Beschreibung Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD5334 Datasheet, Funktion
a 2.5 V to 5.5 V, 500 A, Parallel Interface
Quad Voltage-Output 8-/10-/12-Bit DACs
AD5334/AD5335/AD5336/AD5344*
FEATURES
AD5334: Quad 8-Bit DAC in 24-Lead TSSOP
AD5335: Quad 10-Bit DAC in 24-Lead TSSOP
AD5336: Quad 10-Bit DAC in 28-Lead TSSOP
AD5344: Quad 12-Bit DAC in 28-Lead TSSOP
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Output Range: 0–VREF or 0–2 VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40؇C to +105؇C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 500 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both sup-
ply rails.
The AD5334/AD5335/AD5336/AD5344 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5334 and AD5336 allows the output
range to be set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
On the AD5334, AD5335 and AD5336 an asynchronous CLR
input is also provided. This resets the contents of the Input
Register and the DAC Register to all zeros. These devices also
incorporate a power-on-reset circuit that ensures that the DAC
output powers on to 0 V and remains there until valid data is
written to the device.
The AD5334/AD5335/AD5336/AD5344 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5334 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
VREFA/B
VDD
GAIN
DB... 7
DB0
CS
WR
A0
A1
POWER-ON
RESET
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
INTER-
FACE
LOGIC
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
INPUT
DAC
REGISTER REGISTER
8-B8I-TBIT
DADCAC
AD5334
BUFFER
BUFFER
BUFFER
VOUTA
VOUTB
VOUTC
CLR
LDAC
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
BUFFER
VOUTD
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
*Protected by U.S. Patent Number 5,969,657.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
VREFC/D
PD GND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD5334 Datasheet, Funktion
AD5334/AD5335/AD5336/AD5344
D......B7
DB0
CS
WR
A0
A1
HBEN
AD5335 FUNCTIONAL BLOCK DIAGRAM
VREFA/B
VDD
POWER-ON
RESET
HIGH BYTE
REGISTER
AD5335
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
INTER-
FACE
LOGIC
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
AD5335 PIN CONFIGURATION
VOUTA
VOUTB
VREFC/D 1
24 CLR
VREFA/B 2
23 HBEN
VOUTA 3
22 DB7
VOUTB 4
VOUTC 5
10-BIT
AD5335
21 DB6
20 DB5
VOUTD 6 TOP VIEW 19 DB4
GND 7 (Not to Scale) 18 DB3
CS 8
17 DB2
WR 9
16 DB1
A0 10
15 DB0
A1 11
LDAC 12
14 VDD
13 PD
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
VOUTC
CLR
LDAC
LOW BYTE
REGISTER
RESET
DAC
REGISTER
10-BIT
DAC
BUFFER
VOUTD
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15–22
23
24
Mnemonic
VREFC/D
VREFA/B
VOUTA
VOUTB
VOUTC
VOUTD
GND
CS
WR
A0
A1
LDAC
PD
VDD
DB0–DB7
HBEN
CLR
VREFC/D
PD GND
AD5335 PIN FUNCTION DESCRIPTIONS
Function
Unbuffered Reference Input for DACs C and D.
Unbuffered Reference Input for DACs A and B.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
Output of DAC C. Buffered output with rail-to-rail operation.
Output of DAC D. Buffered output with rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
LSB Address Pin for Selecting which DAC Is to Be Written to.
MSB Address Pin for Selecting which DAC Is to Be Written to.
Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
This pin is used when writing to the device to determine if data is written to the high byte register or the
low byte register.
Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
6REV. 0

6 Page









AD5334 pdf, datenblatt
AD5334/AD5335/AD5336/AD5344
0.2
0.1 TA = 25؇C
VREF = 2V
0
GAIN ERROR
0.1
0.2
0.3
0.4
OFFSET ERROR
0.5
0.6
01 2 3 4 5 6
VDD Volts
Figure 14. Offset Error and Gain
Error vs. VDD
5
5V SOURCE
4
3V SOURCE
3
2
1 3V SINK
5V SINK
0
01 2 3 4 5 6
SINK/SOURCE CURRENT mA
Figure 15. VOUT Source and Sink
Current Capability
600
TA = 25؇C
500
400
300
200
100
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD V
Figure 17. Supply Current vs. Supply
Voltage
0.5
TA = 25؇C
0.4
0.3
0.2
0.1
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD V
Figure 18. Power-Down Current vs.
Supply Voltage
600
500
400
300
200
100
0
ZERO-SCALE
VDD = 5.5V
VDD = 3.6V
TA = 25؇C
VREF = 2V
DAC CODE
FULL SCALE
Figure 16. Supply Current
vs. DAC Code
1800
1600
1400
1200
1000
800
600
VDD = 5V
400
VDD = 3V
200
0
01234
VLOGIC V
Figure 19. Supply Current
vs. Logic Input Voltage
5
CH1
TA = 25؇µCs
VDD = 5V
VREF = 5V
VOUTA
CH2
LDAC
CH1
TA = 25؇C
VDD = 5V
VREF = 2V
VDD
CH2
VOUTA
CH1 1V, CH2 5V, TIME BASE= 1s/DIV
Figure 20. Half-Scale Settling (1/4 to
3/4 Scale Code Change)
CH1 2V, CH2 200mV, TIME BASE = 200s/DIV
Figure 21. Power-On Reset to 0 V
TA = 25؇C
VDD = 5V
VREF = 2V
CH1
VOUTA
CH2
PD
CH1 500mV, CH2 5V, TIME BASE = 1s/DIV
Figure 22. Exiting Power-Down
to Midscale
12
REV. 0

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