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PDF AD5333 Data sheet ( Hoja de datos )
| Número de pieza | AD5333 | |
| Descripción | Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5333 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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a 2.5 V to 5.5 V, 230 A, Parallel Interface
Dual Voltage-Output 8-/10-/12-Bit DACs
AD5332/AD5333/AD5342/AD5343*
FEATURES
AD5332: Dual 8-Bit DAC in 20-Lead TSSOP
AD5333: Dual 10-Bit DAC in 24-Lead TSSOP
AD5342: Dual 12-Bit DAC in 28-Lead TSSOP
AD5343: Dual 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 230 A @ 3 V, 300 A @ 5 V
via PD Pin
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40؇C to +105؇C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 230 µA at 3 V, and feature a power-down pin, PD
that further reduces the current to 80 nA. These devices incor-
porate an on-chip output buffer that can drive the output to
both supply rails, while the AD5333 and AD5342 allow a choice
of buffered or unbuffered reference input.
The AD5332/AD5333/AD5342/AD5343 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5333 and AD5342 allows the output
range to be set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5332/AD5333/AD5342/AD5343 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5332 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
VREFA
VDD
DB... 7
DB0
CS
WR
A0
CLR
LDAC
INTER-
FACE
LOGIC
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
8-BIT
DAC
RESET
VREFB
AD5332
BUFFER
VOUTA
BUFFER
VOUTB
POWER-DOWN
LOGIC
PD GND
*Protected by U.S. Patent Number 5,969,657.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
DB... 7
DB0
CS
WR
A0
CLR
LDAC
AD5332 FUNCTIONAL BLOCK DIAGRAM
AD5332/AD5333/AD5342/AD5343
AD5332 PIN CONFIGURATION
INTER-
FACE
LOGIC
VREFA
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
VDD
AD5332
BUFFER
BUFFER
VOUTA
VOUTB
VREFB 1
20 DB7
VREFA 2
19 DB6
VOUTA 3
18 DB5
VOUTB
GND
CS
WR
4 17 DB4
8-BIT
5 AD5332 16 DB3
6
TOP VIEW 15
(Not to Scale)
DB2
7 14 DB1
A0 8
13 DB0
CLR 9
12 VDD
LDAC 10
11 PD
RESET
POWER-DOWN
LOGIC
VREFB
PD GND
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13–20
Mnemonic
VREFB
VREFA
VOUTA
VOUTB
GND
CS
WR
A0
CLR
LDAC
PD
VDD
DB0–DB7
AD5332 PIN FUNCTION DESCRIPTIONS
Function
Unbuffered reference input for DAC B.
Unbuffered reference input for DAC A.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Address pin for selecting which DAC A and DAC B.
Asynchronous active low control input that clears all input registers and DAC registers to zeros.
Active low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
REV. 0
–5–
5 Page 
Typical Performance Characteristics–AD5332/AD5333/AD5342/AD5343
1.0
TA = 25؇C
VDD = 5V
0.5
0
–0.5
–1.0
0
50 100 150 200 250
CODE
Figure 5. AD5332 Typical INL Plot
3
TA = 25؇C
VDD = 5V
2
1
0
–1
–2
–3
0 200 400 600 800 1000
CODE
Figure 6. AD5333 Typical INL Plot
12
TA = 25؇C
8 VDD = 5V
4
0
–4
–8
–12
0
1000
2000
CODE
3000
4000
Figure 7. AD5342 Typical INL Plot
0.3
TA = 25؇C
VDD = 5V
0.2
0.1
0
–0.1
–0.2
–0.3
0
50 100 150 200 250
CODE
Figure 8. AD5332 Typical DNL Plot
0.6
TA = 25؇C
VDD = 5V
0.4
0.2
0
–0.2
–0.4
–0.6
0
200 400 600 800 1000
CODE
Figure 9. AD5333 Typical DNL Plot
1.0
TA = 25؇C
VDD = 5V
0.5
0
–0.5
–1
0
1000
2000
3000
4000
CODE
Figure 10. AD5342 Typical DNL Plot
1.00
0.75
0.50
VDD = 5V
TA = 25؇C
0.25
0.00
–0.25
–0.50
MAX INL
MAX DNL
MIN DNL
MIN INL
–0.75
–1.00
2
34
VREF – V
5
Figure 11. AD5332 INL and DNL
Error vs. VREF
1.00
0.75
VDD = 5V
VREF = 2V
0.50
MAX DNL MAX INL
0.25
0
–0.25
–0.50
MIN INL MIN DNL
–0.75
–1.00
–40
0 40 80
TEMPERATURE – ؇C
120
Figure 12. AD5332 INL Error and
DNL Error vs. Temperature
1.0
VDD = 5V
VREF = 2V
0.5
0.0
GAIN ERROR
OFFSET ERROR
–0.5
–1.0
–40
0 40 80
TEMPERATURE – ؇C
120
Figure 13. AD5332 Offset Error
and Gain Error vs. Temperature
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD5333.PDF ] | |
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