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AD5332 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5332
Beschreibung Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD5332 Datasheet, Funktion
a 2.5 V to 5.5 V, 230 A, Parallel Interface
Dual Voltage-Output 8-/10-/12-Bit DACs
AD5332/AD5333/AD5342/AD5343*
FEATURES
AD5332: Dual 8-Bit DAC in 20-Lead TSSOP
AD5333: Dual 10-Bit DAC in 24-Lead TSSOP
AD5342: Dual 12-Bit DAC in 28-Lead TSSOP
AD5343: Dual 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 230 A @ 3 V, 300 A @ 5 V
via PD Pin
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40؇C to +105؇C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 230 µA at 3 V, and feature a power-down pin, PD
that further reduces the current to 80 nA. These devices incor-
porate an on-chip output buffer that can drive the output to
both supply rails, while the AD5333 and AD5342 allow a choice
of buffered or unbuffered reference input.
The AD5332/AD5333/AD5342/AD5343 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5333 and AD5342 allows the output
range to be set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5332/AD5333/AD5342/AD5343 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5332 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
VREFA
VDD
DB... 7
DB0
CS
WR
A0
CLR
LDAC
INTER-
FACE
LOGIC
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
8-BIT
DAC
RESET
VREFB
AD5332
BUFFER
VOUTA
BUFFER
VOUTB
POWER-DOWN
LOGIC
PD GND
*Protected by U.S. Patent Number 5,969,657.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD5332 Datasheet, Funktion
AD5332/AD5333/AD5342/AD5343
AD5333 FUNCTIONAL BLOCK DIAGRAM
BUF
GAIN
DB... 9
DB0
CS
WR
A0
CLR
LDAC
VREFA
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
INTER-
FACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
RESET
10-BIT
DAC
10-BIT
DAC
VREFB
VDD
AD5333
BUFFER
VOUTA
BUFFER
VOUTB
POWER-DOWN
LOGIC
PD GND
AD5333 PIN CONFIGURATION
GAIN 1
24 DB9
BUF 2
23 DB8
VREFB 3
22 DB7
VREFA 4
VOUTA 5
10-BIT
AD5333
21 DB6
20 DB5
VOUTB 6 TOP VIEW 19 DB4
GND 7 (Not to Scale) 18 DB3
CS 8
17 DB2
WR 9
16 DB1
A0 10
15 DB0
CLR 11
LDAC 12
14 VDD
13 PD
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15–24
Mnemonic
GAIN
BUF
VREFB
VREFA
VOUTA
VOUTB
GND
CS
WR
A0
CLR
LDAC
PD
VDD
DB0–DB9
AD5333 PIN FUNCTION DESCRIPTIONS
Function
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference input for DAC B.
Reference input for DAC A.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Address pin for selecting between DAC A and DAC B.
Asynchronous active-low control input that clears all input registers and DAC registers to zeros.
Active-low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
10 Parallel Data Inputs. DB9 is the MSB of these 10 bits.
6REV. 0

6 Page









AD5332 pdf, datenblatt
AD5332/AD5333/AD5342/AD5343
0.2
0.1 TA = 25ؠC
VREF = 2V
0
GAIN ERROR
0.1
0.2
0.3
0.4
OFFSET ERROR
0.5
0.6
01 23 4 5 6
VDD Volts
Figure 14. Offset Error and Gain
Error vs. VDD
5
5V SOURCE
4
3V SOURCE
3
2
1 3V SINK
5V SINK
0
01 23 4 5 6
SINK/SOURCE CURRENT mA
Figure 15. VOUT Source and Sink
Current Capability
400
TA = 25؇C
350 VREF = 2V
300
250
VDD = 5.5V
VDD = 3.6V
200
150
100
50
0
ZERO-SCALE
DAC CODE
FULL-SCALE
Figure 16. Supply Current vs. DAC
Code
400
TA = 25؇C
300
200
100
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD V
Figure 17. Supply Current vs. Supply
Voltage
0.5
TA = 25؇C
0.4
0.3
0.2
0.1
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD V
Figure 18. Power-Down Current vs.
Supply Voltage
1600
TA = 25؇C
1400
1200
1000
800
600
400 VDD = 5V
200 VDD = 3V
0
01 23 45
VLOGIC V
Figure 19. Supply Current vs. Logic
Input Voltage
CH2 LDAC
VDD = 5V
TA = 25؇C
CH1
VOUT
CH1 1V, CH2 5V, TIME BASE = 5s/DIV
Figure 20. Half-Scale Settling (1/4 to
3/4 Scale Code Change)
CH1
TA = 25ؠC
VDD = 5V
VREF = 2V
VDD
CH2
VOUTA
CH1 2V, CH2 200mV, TIME BASE = 200s/DIV
Figure 21. Power-On Reset to 0 V
TA = 25ؠC
VDD = 5V
VREF = 2V
CH1
VOUTA
CH2
PD
CH1 500mV, CH2 5V, TIME BASE = 1s/DIV
Figure 22. Exiting Power-Down to
Midscale
12
REV. 0

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