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AD5318 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5318
Beschreibung 8-/10-/12-Bit DACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD5318 Datasheet, Funktion
2.5 V to 5.5 V Octal Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5308/AD5318/AD5328
FEATURES
AD5308: 8 buffered 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL, B version: ±0.75 LSB INL
AD5318: 8 buffered 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL, B version: ±3 LSB INL
AD5328: 8 buffered 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL, B version: ±12 LSB INL
Low power operation: 0.7 mA @ 3 V
Guaranteed monotonic by design over all codes
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Double-buffered input logic
Buffered/unbuffered/VDD reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on reset to 0 V
Programmability
Individual channel power-down
Simultaneous update of outputs (LDAC)
Low power, SPI-®, QSPI-™, MICROWIRE-™, and DSP-
compatible 3-wire serial interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +125°C
Qualified for automotive applications
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP. They operate
from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5308/
AD5318/AD5328 use a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface
standards.
The references for the eight DACs are derived from two
reference pins (one per DAC quad). These reference inputs can
be configured as buffered, unbuffered, or VDD inputs. The parts
incorporate a power-on reset circuit, which ensures that the
DAC outputs power up to 0 V and remain there until a valid
write to the device takes place. The outputs of all DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the current
consumption of the devices to 400 nA at 5 V (120 nA at 3 V).
The eight channels of the DAC may be powered down individually.
All three parts are offered in the same pinout, which allows
users to select the resolution appropriate for their application
without redesigning their circuit board.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2011 Analog Devices, Inc. All rights reserved.






AD5318 Datasheet, Funktion
AD5308/AD5318/AD5328
Table 3. Timing Characteristics1, 2, 3
A, B Version
Parameter
Limit at TMIN, TMAX
t1 33
t2 13
t3 13
t4 13
15
t5 5
t6 4.5
t7 0
t8 50
t9 20
t10 20
t11 0
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +105°C
SYNC to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +125°C
Data set up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK falling edge to LDAC falling edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
SCLK
SYNC
DIN
LDAC1
LDAC2
t8 t4
t6
DB15
t5
t1
t3 t2
t7
DB0
t11
t9
t10
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Interface Timing Diagram
Rev. F | Page 6 of 28

6 Page









AD5318 pdf, datenblatt
AD5308/AD5318/AD5328
35
SS = 300
30
VDD = 3V
VDD = 5V
25
MEAN: 0.693798
20 MEAN: 1.02055
15
10
5
0
0.6 0.7 0.8 0.9 1.0 1.1
IDD (mA)
Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V
2.50
2.49
2.48
2.47
1μs/DIV
Figure 23. AD5328 Major-Code Transition Glitch Energy
10
0
–10
–20
–30
–40
–50
–60
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response)
0.02
TA = 25°C
VDD = 5V
0.01
0
–0.01
–0.02
0
1234
VREF (V)
Figure 25. Full-Scale Error vs. VREF
5
6
100ns/DIV
Figure 26. DAC-to-DAC Crosstalk
Rev. F | Page 12 of 28

12 Page





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