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PDF AD526 Data sheet ( Hoja de datos )
| Número de pieza | AD526 | |
| Descripción | Software Programmable Gain Amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD526 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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a
Software Programmable
Gain Amplifier
AD526
FEATURES
Digitally Programmable Binary Gains from 1 to 16
Two-Chip Cascade Mode Achieves Binary Gain from
1 to 256
Gain Error:
0.01% Max, Gain = 1, 2, 4 (C Grade)
0.02% Max, Gain = 8, 16 (C Grade)
0.5 ppm/؇C Drift Over Temperature
Fast Settling Time
10 V Signal Change:
0.01% in 4.5 s (Gain = 16)
Gain Change:
0.01% in 5.6 s (Gain = 16)
Low Nonlinearity: ؎0.005% FSR Max (J Grade)
Excellent DC Accuracy:
Offset Voltage: 0.5 mV Max (C Grade)
Offset Voltage Drift: 3 V/؇C (C Grade)
TTL-Compatible Digital Inputs
PIN CONFIGURATION
DIG GND 1
16 A1
NULL 2
15 A0
VIN 3
14 CS
NULL 4 AD526 13 CLK
TOP VIEW
ANALOG GND 2 5 (Not to Scale) 12 A2
ANALOG GND 1 6
11 B
–VS 7
VOUT SENSE 8
10 +VS
9 VOUT FORCE
PRODUCT DESCRIPTION
The AD526 is a single-ended, monolithic software program-
mable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8
and 16. It is complete, including amplifier, resistor network
and TTL-compatible latched inputs, and requires no external
components.
Low gain error and low nonlinearity make the AD526 ideal for
precision instrumentation applications requiring programmable
gain. The small signal bandwidth is 350 kHz at a gain of 16. In
addition, the AD526 provides excellent dc precision. The FET-
input stage results in a low bias current of 50 pA. A guaranteed
maximum input offset voltage of 0.5 mV max (C grade) and low
gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using
Analog Devices’ laser trimming technology.
To provide flexibility to the system designer, the AD526 can be
operated in either latched or transparent mode. The force/sense
configuration preserves accuracy when the output is connected
to remote or low impedance loads.
The AD526 is offered in one commercial (0°C to +70°C) grade,
J, and three industrial grades, A, B and C, which are specified
from –40°C to +85°C. The S grade is specified from –55°C to
+125°C. The military version is available processed to MIL-
STD 883B, Rev C. The J grade is supplied in a 16-lead plastic
DIP, and the other grades are offered in a 16-lead hermetic
side-brazed ceramic DIP.
APPLICATION HIGHLIGHTS
1. Dynamic Range Extension for ADC Systems: A single
AD526 in conjunction with a 12-bit ADC can provide
96 dB of dynamic range for ADC systems.
2. Gain Ranging Preamps: The AD526 offers complete digital
gain control with precise gains in binary steps from 1 to 16.
Additional gains of 32, 64, 128 and 256 are possible by cas-
cading two AD526s.
ORDERING GUIDE
Model
Temperature Package
Range
Descriptions
Package
Options
AD526JN
Commercial
AD526AD
Industrial
AD526BD
Industrial
AD526CD
Industrial
AD526SD
Military
AD526SD/883B
Military
5962-9089401MEA* Military
16-Lead Plastic DIP N-16
16-Lead Cerdip D-16
16-Lead Cerdip D-16
16-Lead Cerdip D-16
16-Lead Cerdip D-16
16-Lead Cerdip D-16
16-Lead Cerdip D-16
*Refer to official DESC drawing for tested specifications.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
1000
100
10
10
100 1k 10k
FREQUENCY – Hz
100k
Figure 10. Noise Spectral Density
AD526
0.006
0.004
0.002
0.000
–0.002
–0.004
–60
–20 20
60 100
TEMPERATURE – ؇C
Figure 11. Nonlinearity vs.
Temperature, Gain = 1
140
Figure 12. Wideband Output Noise,
G = 16 (Amplified by 10)
Figure 13. Large Signal Pulse
Response and Settling Time,*
G=1
Figure 14. Small Signal Pulse
Response, G = 1
Figure 15. Large Signal Pulse
Response and Settling Time,*
G=2
Figure 16. Small Signal Pulse
Response, G = 2
Figure 17. Large Signal Pulse
Response and Settling Time,*
G=4
Figure 18. Small Signal Pulse
Response, G = 4
*For Settling Time Traces, 0.01% = 1/2 Vertical Division
REV. D
–5–
5 Page 
OFFSET NULLING
Input voltage offset nulling of the AD526 is best accomplished
at a gain of 16, since the referred-to-input (RTI) offset is ampli-
fied the most at this gain and therefore is most easily trimmed.
The resulting trimmed value of RTI voltage offset typically
varies less than 3 µV across all gain ranges.
Note that the low input current of the AD526 minimizes RTI
voltage offsets due to source resistance.
+VS
0.1F
16 15 14 13 12 11
A1 A0 CS CLK A2 B
LOGIC AND LATCHES
10
OUT
9 FORCE
16 8 4 2 1
GAIN NETWORK
AD526
–
+
VOUT
1 2 3 4 5 6 7 8 OUT
SENSE
VIN
20k⍀
0.1F
–VS
Figure 39. Offset Voltage Null Circuit
OUTPUT CURRENT BOOSTER
The AD526 is rated for a full ± 10 V output voltage swing into
2 kΩ. In some applications, the need exists to drive more cur-
rent into heavier loads. As shown in Figure 40, a high current
booster may be connected “inside the loop” of the SPGA to
provide the required current boost without significantly degrad-
ing overall performance. Nonlinearities, offset and gain inaccu-
racies of the buffer are minimized by the loop gain of the
AD526 output amplifier.
+VS
0.1F
16 15 14 13 12 11
A1 A0 CS CLK A2 B
LOGIC AND LATCHES
10
16 8 4 2 1
OUT
9 FORCE
GAIN NETWORK
AD526
–
+
1 2 3 4 5 6 7 8 OUT
SENSE
0.1F
VIN
–VS
0.01F
HOS-100
0.01F
RL
AD526
CASCADED OPERATION
A cascade of two AD526s can be used to achieve binarily
weighted gains from 1 to 256. If gains from 1 to 128 are needed,
no additional components are required. This is accomplished by
using the B pin as shown in Figure 38. When the B pin is low,
the AD526 is held in a unity gain stage independent of the other
gain code values.
OFFSET NULLING WITH A D/A CONVERTER
Figure 41 shows the AD526 with offset nulling accomplished
with an 8-bit D/A converter (AD7524) circuit instead of the
potentiometer shown in Figure 39. The calibration procedure is
the same as before except that instead of adjusting the potenti-
ometer, the D/A converter corrects for the offset error. This
calibration circuit has a number of benefits in addition to elimi-
nating the trimpot. The most significant benefit is that calibra-
tion can be under the control of a microprocessor and therefore
can be implemented as part of an autocalibration scheme. Sec-
ondly, dip switches or RAM can be used to hold the 8-bit word
after its value has been determined. In Figure 42 the offset null
sensitivity, at a gain of 16, is 80 µV per LSB of adjustment,
which guarantees dc accuracy to the 16-bit performance level.
MSB
LSB
CS
WR
+VS
0.1F
16 15 14 13 12 11
A1 A0 CS CLK A2 B
LOGIC AND LATCHES
10
OUT
9 FORCE
16 8 4 2 1
GAIN NETWORK
AD526
–
+
VOUT
1
+VS VIN
AD581 OR
AD587
+10V
VREF
AD7524
2 3 4 5 6 7 8 OUT
SENSE
3.3M⍀
7.5M⍀
0.1F
–VS
1k⍀
ALL BYPASS CAPACITORS ARE 0.1F
+VS
0.01F
OUT 1
OUT 2
10F
–
AD548
+
0.01F
GND
–VS
Figure 41. Offset Nulling Using a DAC
Figure 40. Current Output Boosting
REV. D
–11–
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AD526.PDF ] | |
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