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AD5235 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5235
Beschreibung Dual 1024-Position Digital Potentiometer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD5235 Datasheet, Funktion
Data Sheet
Nonvolatile Memory, Dual
1024-Position Digital Potentiometer
AD5235
FEATURES
Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Maximum ±8% nominal resistor tolerance error
Low temperature coefficient: 35 ppm/°C
2.7 V to 5 V single supply or ±2.5 V dual supply
SPI-compatible serial interface
Nonvolatile memory stores wiper settings
Power-on refreshed with EEMEM settings
Permanent memory write protection
Resistance tolerance stored in EEMEM
26 bytes extra nonvolatile memory for user-defined
information
1M programming cycles
100-year typical data retention
APPLICATIONS
DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration
GENERAL DESCRIPTION
The AD5235 is a dual-channel, nonvolatile memory,1 digitally
controlled potentiometer2 with 1024-step resolution, offering
guaranteed maximum low resistor tolerance error of ±8%.
The device performs the same electronic adjustment function
as a mechanical potentiometer with enhanced resolution, solid
state reliability, and superior low temperature coefficient per-
formance. The versatile programming of the AD5235 via an
SPI®-compatible serial interface allows 16 modes of operation
and adjustment including scratchpad programming, memory
storing and restoring, increment/decrement, ±6 dB/step log taper
adjustment, wiper setting readback, and extra EEMEM1 for user-
defined information such as memory data for other components,
look-up table, or system identification information.
1 The terms nonvolatile memory and EEMEM are used interchangeably.
2 The terms digital potentiometer and RDAC are used interchangeably.
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SDO
ADDR
DECODE
SERIAL
INTERFACE
PR
POWER-ON
RESET
WP
RDY
EEMEM
CONTROL
RDAC1
REGISTER
AD5235
EEMEM1
RDAC2
REGISTER
EEMEM2
RDAC1
RDAC2
RTOL*
26 BYTES
USER EEMEM
VDD
A1
W1
B1
A2
W2
B2
VSS
GND
*RAB TOLERANCE
Figure 1.
In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC2 register, which sets the
resistance between Terminal W and Terminal A and Terminal W
and Terminal B. This setting can be stored into the EEMEM
and is restored automatically to the RDAC register during
system power-on.
The EEMEM content can be restored dynamically or through
external PR strobing, and a WP function protects EEMEM
contents. To simplify the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at
a time. For logarithmic ±6 dB changes in the wiper setting, the
left or right bit shift command can be used to double or halve the
RDAC wiper setting.
The AD5235 patterned resistance tolerance is stored in the
EEMEM. The actual end-to-end resistance can, therefore, be
known by the host processor in readback mode. The host can
execute the appropriate resistance step through a software
routine that simplifies open-loop applications as well as
precision calibration and tolerance matching applications.
The AD5235 is available in a thin, 16-lead TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.






AD5235 Datasheet, Funktion
AD5235
Data Sheet
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 2.7 V and VDD = 5 V.
Table 2.
Parameter
Clock Cycle Time (tCYC)
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay2
CLK to SDO Data Hold Time
CS High Pulse Width3
CS High to CS High3
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store EEMEM Time4, 5
Read EEMEM Time4
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)6
Preset Response Time to Wiper Setting6
Power-On EEMEM Restore Time6
FLASH/EE MEMORY RELIABILITY
Endurance7
Data Retention8
Symbol
t1
t2
t3
t4, t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t16
t17
tPRW
tPRESP
tEEMEM
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
Applies to Instructions 0x2, 0x3
Applies to Instructions 0x8, 0x9, 0x10
PR pulsed low to refresh wiper positions
TA = 25°C
Min Typ1 Max Unit
20 ns
10 ns
1 tCYC
10 ns
5 ns
5 ns
40 ns
50 ns
50 ns
0 ns
10 ns
4 tCYC
0 ns
0.15 0.3
ms
15 50
ms
7 30
µs
10 ns
50 ns
30 µs
30 µs
1
100
100
MCycles
kCycles
Years
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3 Valid for commands that do not activate the RDY pin.
4 The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;
CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 µs.
5 Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.
6 Not shown in Figure 2 and Figure 3.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.
8 Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev. F | Page 6 of 32

6 Page









AD5235 pdf, datenblatt
AD5235
3
0
RAB = 25k
–3
RAB = 250k
–6
f–3dB = 12kHz
–9
VDD/VSS = ±2.5V
VA = 1V rms
D = MIDSCALE
–12
1k 10k
f–3dB = 125kHz
100k
1M
FREQUENCY (Hz)
Figure 17. −3 dB Bandwidth vs. Resistance (See Figure 33)
0
CODE 0x200
–10 0x100
0x080
–20
0x040
0x020
–30
0x010
–40 0x008
0x004
0x002
–50
0x001
–60
1k
10k 100k 1M
FREQUENCY (Hz)
Figure 18. Gain vs. Frequency vs. Code, RAB = 25 kΩ (See Figure 33)
0
CODE 0x200
–10 0x100
0x080
–20
0x040
0x020
–30
0x010
–40 0x008
0x004
–50 0x002
0x001
–60
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 19. Gain vs. Frequency vs. Code, RAB = 250 kΩ (See Figure 33)
Data Sheet
0
VDD = 5V ± 10% AC
–10
VSS = 0V, VA = 4V, VB = 0V
MEASURED AT VW WITH CODE = 0x200
TA = 25°C
–20
–30 RAB = 250k
–40 RAB = 25k
–50
–60
–70
–80
10
100 1k 10k 100k
FREQUENCY (Hz)
Figure 20. PSRR vs. Frequency
1M
VDD
VW (FULL SCALE)
10µs/DIV
VDD = 5V
VA = 5V
VB = 0V
TA = 25°C
1V/DIV
Figure 21. Power-On Reset
2.5196
2.516
VDD = VSS = 5V
CODE = 0x200 TO 0x1FF
2.512
2.508
2.504
2.500
2.496
2.492
2.488
2.484
2.4796
0
20 40 60 80 100 120
TIME (µs)
Figure 22. Midscale Glitch Energy, RAB = 25 kΩ
144
Rev. F | Page 12 of 32

12 Page





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