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AD5161 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5161
Beschreibung 256-Position SPI/I2C Selectable Digital Potentiometer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD5161 Datasheet, Funktion
Data Sheet
FEATURES
256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Pin selectable SPI/I2C compatible interface
Extra package address decode pin AD0
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 8 µA
Wide operating temperature −40°C to +125°C
SDO output allows multiple device daisy-chaining
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5161 provides a compact 3 mm × 4.9 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
The wiper settings are controllable through a pin selectable SPI
or I2C compatible digital interface, which can also be used to
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I2C mode,
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.
256-Position SPI/I2C Selectable
Digital Potentiometer
AD5161
FUNCTIONAL BLOCK DIAGRAM
VDD SDO/NC
SDI/SDA
CLK/SCL
DIS
CS/AD0
SPI OR I2C
INTERFACE
A
W
WIPER
REGISTER
B
GND
Figure 1.
PIN CONFIGURATION
A1
10 W
B 2 AD5161 9 VDD
CS/ADO 3 TOP VIEW 8 DIS
SDO/NC 4 (Not to Scale) 7 GND
SDI/SDA 5
6 CLK/SCL
Figure 2.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2012 Analog Devices, Inc. All rights reserved.






AD5161 Datasheet, Funktion
AD5161
ABSOLUTE MAXIMUM RATINGS1
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Value
VDD to GND
VA, VB, VW to GND
IMAX1
Digital Inputs and Output Voltage to GND
–0.3 V to +7 V
VDD
±20 mA
0 V to +7 V
Operating Temperature Range
–40°C to +125°C
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
150°C
–65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C
Thermal Resistance2
θJA (10-Lead MSOP)
200°C/W
NOTES
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 6 of 20

6 Page









AD5161 pdf, datenblatt
AD5161
Data Sheet
TEST CIRCUITS
Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables.
5V
DUT
A
V+ W
B
V+ = VDD
1LSB = V+/2N
VMS
Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT
DUT
A
W
B
IW
VMS
OFFSET
GND
OP279
VIN
W
A DUT
OFFSET
BIAS
B
VOUT
Figure 33. Test Circuit for Noninverting Gain
A
VIN DUT
OFFSET
GND
2.5V
B
W
+15V
AD8610
–15V
VOUT
Figure 29. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
VMS2
DUT
A
W
B
IW = VDD / RNOMINAL
VW
VMS1 RW = [VMS1 – VMS2]/ IW
Figure 34. Test Circuit for Gain vs. Frequency
DUT
W
B
RSW =
0.1V
ISW
CODE = 0x00
ISW 0.1V
VSS TO VDD
Figure 30. Test Circuit for Wiper Resistance
VA
VDD A
V+ W
B
( )V+= VDD 10%
PSRR (dB) = 20 LOG
V MS
V DD
PSS (%/%) = VMS%
V DD%
VMS
Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
OFFSET
GND
A DUT B
VIN W
OFFSET
BIAS
5V
OP279
VOUT
Figure 32. Test Circuit for Inverting Gain
Figure 35. Test Circuit for Incremental ON Resistance
NC
VDD DUT
VSS GND
A
W
B
ICM
VCM
NC NC = NO CONNECT
Figure 36. Test Circuit for Common-Mode Leakage Current
Rev. B | Page 12 of 20

12 Page





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