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AD7530 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer AD7530
Beschreibung 10-Bit/ 12-Bit/ Multiplying D/A Converters
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 9 Seiten
AD7530 Datasheet, Funktion
AD7520, AD7530,
AD7521, AD7531
August 1997
10-Bit, 12-Bit, Multiplying D/A Converters
Features
Description
• AD7520/AD7530, 10-Bit Resolution; 8-Bit, 9-Bit and
10-Bit Linearity
• AD7521/AD7531, 12-Bit Resolution; 8-Bit, 9-Bit and
10-Bit Linearity
• Low Power Dissipation (Max) . . . . . . . . . . . . . . . .20mW
• Low Nonlinearity Tempco at 2ppm of FSR/oC
• Current Settling Time to 0.05% of FSR . . . . . . . . 1.0µs
• Supply Voltage Range . . . . . . . . . . . . . . . . ±5V to +15V
• TTL/CMOS Compatible
• Full Input Static Protection
• /883B Processed Versions Available
The AD7520/AD7530 and AD7521/AD7531 are monolithic,
high accuracy, low cost 10-bit and 12-bit resolution,
multiplying digital-to-analog converters (DAC). Intersil’
thin-film on CMOS processing gives up to 10-bit accuracy
with TTL/CMOS compatible operation. Digital inputs are fully
protected against static discharge by diodes to ground and
positive supply.
Typical applications include digital/analog interfacing,
multiplication and division, programmable power supplies,
CRT character generation, digitally controlled gain circuits,
integrators and attenuators, etc.
The AD7530 and AD7531 are identical to the AD7520 and
AD7521, respectively, with the exception of output leakage
current and feedthrough specifications.
Ordering Information
PART NUMBER
AD7520JN, AD7530JN
AD7520KN, AD7530KN
AD7521JN, AD7531JN
AD7521KN, AD7531KN
AD7520LN, AD7530LN
AD7521LN, AD7531LN
AD7520JD
AD7520KD
AD7520LD
AD7520SD, AD7520SD/883B
AD7520UD, AD7520UD/883B
LINEARITY (INL, DNL)
0.2% (8-Bit)
0.1% (9-Bit)
0.2% (8-Bit)
0.1% (9-Bit)
0.05% (10-Bit)
0.05% (10-Bit)
0.2% (8-Bit)
0.1% (9-Bit)
0.05% (10-Bit)
0.2% (8-Bit)
0.05% (10-Bit)
Pinouts
AD7520, AD7530
(CERDIP, PDIP)
TOP VIEW
IOUT1 1
IOUT2 2
GND 3
BIT 1 (MSB) 4
BIT 2 5
BIT 3 6
BIT 4 7
BIT 5 8
16 RFEEDBACK
15 VREF
14 V+
13 BIT 10 (LSB)
12 BIT 9
11 BIT 8
10 BIT 7
9 BIT 6
TEMP. RANGE (oC)
PACKAGE
0 to 70
16 Ld PDIP
0 to 70
16 Ld PDIP
0 to 70
18 Ld PDIP
0 to 70
18 Ld PDIP
-40 to 85
16 Ld PDIP
-40 to 85
18 Ld PDIP
-25 to 85
16 Ld CERDIP
-25 to 85
16 Ld CERDIP
-25 to 85
16 Ld CERDIP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld CERDIP
PKG. NO.
E16.3
E16.3
E18.3
E18.3
E16.3
E18.3
F16.3
F16.3
F16.3
F16.3
F16.3
AD7521, AD7531
(PDIP)
TOP VIEW
IOUT1 1
IOUT2 2
GND 3
BIT 1 (MSB) 4
BIT 2 5
BIT 3 6
BIT 4 7
BIT 5 8
BIT 6 9
18 RFEEDBACK
17 VREF
16 V+
15 BIT 12 (LSB)
14 BIT 11
13 BIT 10
12 BIT 9
11 BIT 8
10 BIT 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
10-7
File Number 3104.1






AD7530 Datasheet, Funktion
AD7520, AD7530, AD7521, AD7531
Applications
Unipolar Binary Operation
The circuit configuration for operating the AD7520 in unipo-
lar mode is shown in Figure 8. Similar circuits can be used
for AD7521, AD7530 and AD7531. With positive and nega-
tive VREF values the circuit is capable of 2-Quadrant multipli-
cation. The “Digital Input Code/Analog Output Value” table
for unipolar mode is given in Table 1.
VREF
+15V
BIT 1 (MSB)
DIGITAL
INPUT
BIT 10 (LSB)
15 14
4 16
5
AD7520 1
13 3 2
RFEEDBACK
IOUT1
IOUT2
GND
-
6
+
VOUT
FIGURE 8. UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
TABLE 1. CODE TABLE - UNlPOLAR BINARY OPERATION
DIGITAL INPUT
1111111111
1000000001
1000000000
0111111111
0000000001
0000000000
NOTES:
1. LSB = 2-N VREF.
2. N = 10 for 7520, 7530;
N = 12 for 7521, 7531.
ANALOG OUTPUT
-VREF (1-2-N)
-VREF (1/2 + 2-N)
-VREF/2
-VREF (1/2-2-N)
-VREF (2-N)
0
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1-2-N) reading. (N = 10 for
AD7520/30 and N = 12 for AD7521/31).
3. To decrease VOUT, connect a series resistor (0 to 250)
between the reference voltage and the VREF terminal.
4. To increase VOUT, connect a series resistor (0 to 250) in
the IOUT1 amplifier feedback loop.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7520 in the
bipolar mode is given in Figure 9. Similar circuits can be
used for AD7521, AD7530 and AD7531. Using offset binary
digital input codes and positive and negative reference volt-
age values, 4-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.
VREF
BIT 1
(MSB)
BIT 10
(LSB)
+15V
R3
10M
15 14
4 16
5
AD7520 1
RFEEDBACK
IOUT1
IOUT2 R1 10K R2 10K
13 3 2
- 0.01% 0.01%
6
+
-
6
+
FIGURE 9. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
TABLE 2. BlPOLAR (OFFSET BINARY) CODE TABLE
DIGITAL INPUT
1111111111
1000000001
1000000000
0111111111
0000000001
0000000000
NOTES:
1. LSB = 2-(N-1) VREF.
ANALOG OUTPUT
-VREF (1-2-(N-1))
-VREF (2-(N-1))
0
VREF (2-(N-1))
VREF (1-2-(N-1))
VREF
2. N = 10 for 7520, 7521;
N = 12 for 7530, 7531.
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic 0”
input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity of
IOUT2 current and the transconductance amplifier at IOUT1 out-
put sums the two currents. This configuration doubles the out-
put range. The difference current resulting at zero offset binary
code, (MSB = “Logic 1”, All other bits = “Logic 0”), is corrected
by using an external resistor, (10M), from VREF to IOUT2.
Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Connect all digital inputs to “Logic 1”.
3. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at
IOUT2 amplifier output.
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
5. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV at
VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1-2-(N-1) volts reading. (N = 10 for
AD7520 and AD7530, and N = 12 for AD7521 and AD7531).
3. To increase VOUT, connect a series resistor of up to 250
between VOUT and RFEEDBACK.
4. To decrease VOUT, connect a series resister of up to 250
between the reference voltage and the VREF terminal.
10-12

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