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AD7523 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer AD7523
Beschreibung 8-Bit/ Multiplying D/A Converters
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 9 Seiten
AD7523 Datasheet, Funktion
AD7523, AD7533
August 1997
8-Bit, Multiplying D/A Converters
Features
Description
• 8-Bit, 9-Bit and 10-Bit Linearity
• Low Gain and Linearity Temperature Coefficients
• Full Temperature Range Operation
• Static Discharge Input Protection
• TTL/CMOS Compatible
• Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +5V to +15V
• Fast Settling Time at 25oC . . . . . . . . . . . . 150ns (Max)
• Four Quadrant Multiplication
• AD7533 Direct AD7520 Equivalent
The AD7523 and AD7533 are monolithic, low cost, high
performance, 8-bit and 10-bit accurate, multiplying digital-to-
analog converter (DAC), in a 16 pin DIP.
Intersil’ thin film resistors on CMOS circuitry provide 10-bit
resolution (8-bit, 9-bit and 10-bit accuracy), with TTL/CMOS
compatible operation.
The AD7523 and AD7533s accurate four quadrant
multiplication, full military temperature range operation, full
input protection from damage due to static discharge by
clamps to V+ and GND, and very low power dissipation
make it a very versatile converter.
Low noise audio gain controls, motor speed controls,
digitally controlled gain and digital attenuators are a few of
the wide range of applications of the AD7523 and AD7533.
Ordering Information
PART NUMBER
LINEARITY (INL, DNL)
AD7523JN, AD7533JN
0.2% (8-Bit)
AD7523KN, AD7533KN
0.1% (9-Bit)
AD7523LN, AD7533LN
0.05% (10-Bit)
TEMP. RANGE (oC)
PACKAGE
0 to 70
16 Ld PDIP
0 to 70
16 Ld PDIP
0 to 70
16 Ld PDIP
PKG. NO.
E16.3
E16.3
E16.3
Pinout
AD7523, AD7533
(PDIP)
TOP VIEW
IOUT1 1
IOUT2 2
GND 3
BIT 1 (MSB) 4
BIT 2 5
BIT 3 6
BIT 4 7
BIT 5 8
16 RFEEDBACK
15 VREF IN
14 V+
NC/BIT 10
13 (NOTE 1)
12 NC/BIT 9
(NOTE 1)
11 BIT 8
10 BIT 7
9 BIT 6
Functional Block Diagram
VREF IN
(15)
20k
10k
20k
10k
20k
10k
20k
SPDT
NMOS
SWITCHES
MSB
(4)
BIT 2
(5)
BIT 3
(6)
10k
20k
20k
(3)
10k
IOUT2 (2)
IOUT1 (1)
RFEEDBACK
(16)
NOTE:
1. NC for AD7523 only.
NOTE: Switches shown for digital inputs “High”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
10-8
File Number 3105.1






AD7523 Datasheet, Funktion
AD7523, AD7533
Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Connect all digital inputs to “Logic 1”.
3. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at
IOUT2 amplifier output.
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to
“Logic 0”.
5. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV
at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (11/28) volts reading.
3. To increase VOUT, connect a series resistor, R2, of up to
250between VOUT and RFEEDBACK.
4. To decrease VOUT, connect a series resistor, R1, of up to
250between the reference voltage and the VREF
terminal.
Bipolar (Offset Binary) Operation - AD7533
The circuit configuration for operating the AD7533 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage val-
ues, 4-Quadrant multiplication can be realized. The “Digital
Input Code/Analog Output Value” table for bipolar mode is
given in Table 4.
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic 0”
input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity of
IOUT2 current and the transconductance amplifier at IOUT1
output sums the two currents. This configuration doubles the
output range. The difference current resulting at zero offset
binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is cor-
rected by using an external resistor, (10M), from VREF to
IOUT2.
TABLE 4. UNlPOLAR BINARY CODE - AD7533
DIGITAL INPUT
MSB LSB
(NOTE 1)
NOMINAL ANALOG OUTPUT
1111111111
- VR E F  55----11---12-- 
1000000001
- VR E F  5----11---2-- 
1000000000
0
0111111111
+ VR E F  5----11---2-- 
0000000001
+ VR E F  55----11---12-- 
0000000000
+ VR E F  55----11---22-- 
NOTES:
1. VOUT as shown in the Functional Diagram.
2. Nominal Full Scale for the circuit of Figure 6 is given by:
FSR = VREF1--5--0--1-2--2--3-  .
3. Nominal LSB magnitude for the circuit of Figure 3 is given by:
LSB = VREF5----11---2-- .
DIGITAL
INPUT
MAGNITUDE
BITS
±10V
BIPOLAR
ANALOG INPUT
V+
VREF
MSB
LSB
15 14
4 16
AD7533 1
13 3
GND
2
RFEEDBACK
OUT1
OUT2
-
6
+
SIGN BIT
10K 10K
-
5K 6
+
1/2 IH5140
FIGURE 4. 10-BIT AND SIGN MULTIPLYING DAC
VOUT
10-13

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