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PDF AD7490 Data sheet ( Hoja de datos )
| Número de pieza | AD7490 | |
| Descripción | 12-Bit ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
16-Channel, 1 MSPS, 12-Bit ADC
with Sequencer in 28-Lead TSSOP
AD7490
FEATURES
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power at maximum throughput rates
5.4 mW maximum at 870 kSPS with 3 V supplies
12.5 mW maximum at 1 MSPS with 5 V supplies
16 (single-ended) inputs with sequencer
Wide input bandwidth
69.5 dB SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface, SPI/QSPI™/MICROWIRE™/
DSP compatible
Full shutdown mode: 0.5 µA maximum
28-lead TSSOP and 32-lead LFCSP packages
GENERAL DESCRIPTION
The AD7490 is a 12-bit high speed, low power, 16-channel,
successive approximation ADC. The part operates from a single
2.7 V to 5.25 V power supply and features throughput rates up
to 1 MSPS. The part contains a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 1 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock signal, allowing the device to
easily interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS, and conversion is also
initiated at this point. There are no pipeline delays associated
with the part.
The AD7490 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. For maximum
throughput rates, the AD7490 consumes just 1.8 mA with 3 V
supplies, and 2.5 mA with 5 V supplies.
By setting the relevant bits in the control register, the analog
input range for the part can be selected to be a 0 V to REFIN
input or a 0 V to 2 × REFIN input, with either straight binary
or twos complement output coding. The AD7490 features 16
single-ended analog inputs with a channel sequencer to allow a
preprogrammed selection of channels to be converted sequen-
tially. The conversion time is determined by the SCLK
FUNCTIONAL BLOCK DIAGRAM
VDD
REFIN
AD7490
VIN0
T/H
INPUT
MUX
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
VIN15
SEQUENCER
CONTROL
LOGIC
AGND
Figure 1.
SCLK
DOUT
DIN
CS
VDRIVE
frequency because this is also used as the master clock to
control the conversion.
The AD7490 is available in a 32-lead LFCSP and a 28-lead
TSSOP package.
PRODUCT HIGHLIGHTS
1. The AD7490 offers up to 1 MSPS throughput rates. At
maximum throughput with 3 V supplies, the AD7490
dissipates just 5.4 mW of power.
2. A sequence of channels can be selected, through which the
AD7490 cycles and converts.
3. The AD7490 operates from a single 2.7 V to 5.25 V supply.
The VDRIVE function allows the serial interface to connect
directly to either 3 V or 5 V processor systems independent
of VDD.
4. The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Power consumption is 0.5 µA, maximum,
when in full shutdown.
5. The part features a standard successive approximation
ADC with accurate control of the sampling instant via a CS
input and once off conversion control.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7490
Data Sheet
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN+3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD 4
Normal Mode (Static)
Normal Mode (Operational)
(fS = Maximum Throughput)
Auto Standby Mode
Auto Shutdown Mode
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
Auto Standby Mode (Static)
Auto Shutdown Mode (Static)
Full Shutdown Mode
Test Conditions/Comments
VIN = 0 V or VDRIVE
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V
ISINK = 200 µA
WEAK/TRI bit set to 0
WEAK/TRI bit set to 0
Coding bit set to 1
Coding bit set to 0
16 SCLK cycles, SCLK = 20 MHz
Sine wave input
Full-scale step input
VDD = 5 V (see the Serial Interface
section)
Digital inputs = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 500 kSPS
Static
fSAMPLE = 250 kSPS
Static
SCLK on or off
VDD = 5 V, fSCLK = 20 MHz
VDD = 3 V, fSCLK = 20 MHz
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Min Typ Max Unit
0.7 × VDRIVE
±0.01
0.3 × VDRIVE
±1
10
V
V
µA
pF
VDRIVE − 0.2
0.4
±10
10
Straight (Natural) Binary
Twos Complement
V
V
µA
pF
800 ns
300 ns
300 ns
1 MSPS
2.7
2.7
600
1.55
960
0.02
5.25 V
5.25 V
µA
2.5 mA
1.8 mA
mA
100 µA
µA
0.5 µA
0.5 µA
12.5 mW
5.4 mW
460 µW
276 µW
2.5 µW
1.5 µW
2.5 µW
1.5 µW
1 Specifications apply for fSCLK up to 20 MHz. However, for serial interfacing requirements, see the Timing Specifications section.
2 See the Terminology section.
3 Guaranteed by characterization.
4 See the Power vs. Throughput Rate section.
Rev. D | Page 4 of 28
5 Page 
AD7490
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 … 000) to
(00 … 001) from the ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 … 110) to
(111 … 111) from the ideal (that is, REFIN − 1 LSB) after the
offset error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Zero Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × REFIN input range with −REFIN
to +REFIN biased about the REFIN point. It is the deviation of the
midscale transition (all 0s to all 1s) from the ideal VIN voltage,
that is, REFIN − 1 LSB.
Zero Code Error Match
This is the difference in zero code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular the 2 × REFIN input range with −REFIN to
+REFIN biased about the REFIN point. It is the deviation of the
last code transition (011 … 110) to (011 … 111) from the ideal
(that is, +REFIN − 1 LSB) after the zero code error has been
adjusted out.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × REFIN input range with −REFIN
to +REFIN biased about the REFIN point. It is the deviation of the
first code transition (100 … 000) to (100 … 001) from the ideal
(that is, −REFIN + 1 LSB) after the zero code error has been
adjusted out.
Data Sheet
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 400 kHz sine wave signal to all 15 nonselected input
channels and determining how much that signal is attenuated in
the selected channel with a 50 kHz signal. This specification is
the worst case across all 16 channels for the AD7490.
PSR (Power Supply Rejection)
Variations in power supply affect the full scale transition, but
not the converter linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value. (see
the Typical Performance Characteristics section).
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track on the 14th
SCLK falling edge. Track-and-hold acquisition time is the
minimum time required for the track-and-hold amplifier to
remain in track mode for its output to reach and settle to within
±1 LSB of the applied input signal, given a step change to the
input signal.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the analog-to-digital converter. The signal is the rms
amplitude of the fundamental. Noise is the sum of all nonfunda-
mental signals up to half the sampling frequency (fS/2), excluding
dc. The ratio is dependent on the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) (dB) = 6.02N + 1.76
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7490, it is defined as
THD(dB) = 20 × log
V22 + V32 + V42 + V52 + V62
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Rev. D | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD7490.PDF ] | |
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