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AD7450 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7450
Beschreibung Differential Input/ 1MSPS/ 12-Bit ADC in SO-8 and S0-8
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD7450 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
Differential Input, 1MSPS,
12-Bit ADC in µSO-8 and S0-8
AD7450
FEATURES
Fast Throughput Rate: 1MSPS
Specified for VDD of 3 V and 5 V
Low Power at max Throughput Rate:
3 mW typ at 833kSPS with 3 V Supplies
8 mW typ at 1MSPS with 5 V Supplies
Fully Differential Analog Input
Wide Input Bandwidth:
70dB SINAD at 300kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface - SPITM/QSPITM/
MicroWireTM/ DSP Compatible
Powerdown Mode: 1µA max
8 Pin µSOIC and SOIC Packages
APPLICATIONS
Transducer Interface
Battery Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
GENERAL DESCRIPTION
The AD7450 is a 12-bit, high speed, low power, succes-
sive-approximation (SAR) analog-to-digital converter
featuring a fully differential analog input. It operates from
a single 3 V or 5 V power supply and features throughput
rates up to 833kSPS or 1MSPS respectively.
This part contains a low-noise, wide bandwidth, differen-
tial track and hold amplifier (T/H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MHz typically. The reference voltage for the
AD7450 is applied externally to the VREF pin and can be
varied from 100 mV to 2.5 V depending on the power
supply and to suit the application. The value of the refer-
ence voltage determines the common mode voltage range
of the part. With this truly differential input structure and
variable reference input, the user can select a variety of
input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock allowing the device to inter-
face with Microprocessors or DSPs. The input signals are
sampled on the falling edge of CS and the conversion is
also initiated at this point.
MicroWire is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
REV. PrJ 27/02/02
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN-
VREF
T/H
12-BIT SUCCESSIVE
APPROXIMATION
A DC
A D7450
CONTROL
LOGIC
SCLK
SDATA
CS
GND
The SAR architecture of this part ensures that there are
no pipeline delays.
The AD7450 uses advanced design techniques to achieve
very low power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1.Operation with either 3 V or 5 V power supplies.
2.High Throughput with Low Power Consumption.
With a 3V supply, the AD7450 offers 3mW typ power
consumption for 833kSPS throughput.
3.Fully Differential Analog Input.
4.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. This
part also features a shutdown mode to maximize power
efficiency at lower throughput rates.
5.Variable Voltage Reference Input.
6.No Pipeline Delay.
7.Accurate control of the sampling instant via a CS input
and once off conversion control.
8. ENOB > 8 bits typ with 100mV Reference.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






AD7450 Datasheet, Funktion
AD7450
PRELIMINARY TECHNICAL DATA
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion)
at the output of the ADC. The signal is the rms amplitude
of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent on the number
of quantization levels in the digitization process; the more
levels, the smaller the quantization noise. The theoretical
signal to (noise + distortion) ratio for an ideal N-bit con-
verter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7450, it
is defined as:
THD (dB ) = 20 log
V
2
2
+
V
2
3
+
V
2
4
+
V
2
5
+
V
2
6
V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second to
the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7450 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while
the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the
sampling clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample to sample variation in the effective
point in time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input fre-
quency at which the amplitude of the reconstructed
fundamental is reduced by 0.1dB or 3dB for a full scale
input.
Common Mode Rejection Ratio (CMRR)
The Common Mode Rejection Ratio is defined as the
ratio of the power in the ADC output at full-scale fre-
quency, f, to the power of a 200mV p-p sine wave applied
to the Common Mode Voltage of VIN+ and VIN- of fre-
quency fs:
CMRR (dB) = 10log(Pf/Pfs)
Pf is the power at the frequncy f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Zero Code Error
This is the deviation of the midscale code transition (111...111
to 000...000) from the ideal VIN+-VIN - (i.e., 0LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+-VIN- (i.e., +VREF - 1LSB), after
the Zero Code Error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+-VIN - (i.e., -VREF + 1LSB), after
the Zero Code Error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode on the
13th SCLK rising edge (see the “Serial Interface Sec-
tion”). The track/hold acquisition time is the minimum
time required for the track and hold amplifier to remain in
track mode for its output to reach and settle to within 0.5
LSB of the applied input signal.
Power Supply Rejection (PSR)
The power supply rejection ratio is defined as the ratio of
the power in the ADC output at full-scale frequency, f, to
the power of a 200mV p-p sine wave applied to the ADC
VDD supply of frequency fs.
PSRR (dB) = 10 log (Pf/Pfs)
Pf is the power at frequency f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
–6– REV. PrJ

6 Page









AD7450 pdf, datenblatt
AD7450
PRELIMINARY TECHNICAL DATA
011...111
011...110
1LSB = 2xVREF/4096
000...001
000...000
111...111
100...010
100...001
100...000
-VREF + 1LSB
0LSB
+VREF - 1LSB
ANALOG INPUT
(VIN+- VIN-)
Figure 5. AD7450 Ideal Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the
AD7450 for both 5 V and 3 V supplies. In this setup the
GND pin is connected to the analog ground plane of the
system. The VREF pin is connected to either a 2.5 V or a
1.25 V decoupled reference source depending on the
power supply, to set up the analog input range. The com-
mon mode voltage has to be set up externally and is the
value that the two inputs are centered on. For more details
on driving the differential inputs and setting up the com-
mon mode, see the ‘Driving Differential Inputs’ section.
The conversion result for the ADC is output in a 16-bit
word consisting of four leading zeros followed by the
MSB of the 12-bit result. For applications where power
consumption is of concern, the power-down mode should
be used between conversions or bursts of several conver-
sions to improve power performance. See ‘Modes of
Operation’ section.
VREF
P-to-P
VREF
P-to-P
0.1µF
10µF
+3V/+5V
SUPPLY
SERIAL
INTERFACE
VDD
CM* VIN+
AD7450
CM* VIN-
VREF
SCLK
SDATA
CS
GND
µC/µP
1.25V/2.5V
VREF
0.1µF
THE ANALOG INPUT
The analog input of the AD7450 is fully differential. Dif-
ferential signals have a number of benefits over single
ended signals including noise immunity based on the
device’s common mode rejection, improvements in distor-
tion performance, doubling of the device’s available
dynamic range and flexibility in input ranges and bias
points.
Figure 7 defines the fully differential analog input of the
AD7450.
COMMON
MODE
VOLTAGE
VREF
P-to-P
VREF
P-to-P
VIN+
AD7450
VIN-
Figure 7. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN- pins (i.e.
VIN+ - VIN-). VIN+ and VIN- are simultaneously driven by
two signals each of amplitude VREF that are 180° out of
phase. The amplitude of the differential signal is therefore
-VREF to +VREF peak-to-peak (i.e. 2 x VREF). This is re-
gardless of the common mode (CM). The common mode
is the average of the two signals, i.e. (VIN+ + VIN-)/2 and
is therefore the voltage that the two inputs are centered on.
This results in the span of each input being CM ± VREF/2.
This voltage has to be set up externally and its range var-
ies with VREF. As the value of VREF increases, the
common mode range decreases. When driving the inputs
with an amplfier, the actual common mode range will be
determined by the amplifier’s output voltage swing.
Figure 8 shows how the common mode range varies with
VREF for a 5 V power supply and figure 9 shows an ex-
ample of the common mode range when using the
AD8138 differential amplifer to drive the analog inputs.
The common mode must be in this range to guarantee the
specifications. With a 3V power supply, the Common
Mode range is TBD.
For ease of use, the common mode can be set up to be
equal to VREF, resulting in the differential signal being
±VREF centered on VREF. When a conversion takes place,
the common mode is rejected resulting in a virtually noise
free signal of amplitude -VREF to +VREF corresponding to
he digital codes of 0 to 4095.
* CM - COMMON MODE VOLTAGE
Figure 6. Typical Connection Diagram
–12–
REV. PrJ

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