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AD73460 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD73460
Beschreibung Six-Input Channel Analog Front End
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD73460 Datasheet, Funktion
a
FEATURES
AFE PERFORMANCE
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
72 dB SNR
64 kS/s Maximum Sample Rate
–80 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel)
Programmable Input Gain
Single Supply Operation
On-Chip Reference
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
Six-Input Channel
Analog Front End
AD73460
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
AD73460
MEMORY
16K PM 16K DM
(OPTIONAL (OPTIONAL
8K) 8K)
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
ADSP-2100 BASE
ARCHITECTURE
REF
SERIAL PORT
SPORT 2
ADC1 ADC2 ADC3 ADC4 ADC5 ADC6
ANALOG FRONT END
SECTION
GENERAL DESCRIPTION
The AD73460 is a six-input channel analog front-end processor
for general-purpose applications including industrial power meter-
ing or multichannel analog inputs. It features six 16-bit A/D
conversion channels, each of which provides 72 dB signal-to-noise
ratio over a dc-to-2 kHz signal bandwidth. Each channel also
features a programmable input gain amplifier (PGA) with gain
settings in eight stages from 0 dB to 38 dB.
The AD73460 is particularly suitable for industrial power metering
as each channel samples synchronously, ensuring that there is
no (phase) delay between the conversions. The AD73460 also
features low group delay conversions on all channels.
An on-chip reference voltage of 1.25 V is included. The sampling
rate of the device is programmable with separate settings
offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of input channels by cas-
cading an extra AFE external to the AD73460.
The AD73460s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
The AD73460-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM and 16K
(16-bit) of data RAM. The AD73460-40 integrates 40K bytes
of on-chip memory configured as 8K words (24-bit) of program
RAM and 8K (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery-operated
portable equipment. The AD73460 is available in a 119-ball
PBGA package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






AD73460 Datasheet, Funktion
AD73460
TIMING CHARACTERISTICSAFE SECTION1
(AVDD = 3 V to 3.6 V; DVDD = 3 V to 3.6 V; AGND = DGND = 0 V;
TA = TMlN to TMAX, unless otherwise noted.)
Parameter
Limit at
TA = 20؇C to +85؇C
Unit
Description
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
See Figure 1
AMCLK Period
AMCLK Width High
AMCLK Width Low
See Figures 3 and 4
SCLK Period (SCLK = AMCLK)
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from AMCLK
NOTES
1For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . 0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . 0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . 0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 20°C to +85°C
Storage Temperature Range . . . . . . . . . . . . 20°C to +125°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
PBGA, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W
Reflow Soldering
Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . 225°C
Time at Maximum Temperature . . . . . . . . . . . . . . . 15 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Model
AD73460BB-80
AD73460BB-40
ORDERING GUIDE
Temperature
Range
Package
Description
20°C to +85°C
20°C to +85°C
119-Ball Plastic Grid Array
119-Ball Plastic Grid Array
Package
Options
B-119
B-119
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD73460 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6– REV. 0

6 Page









AD73460 pdf, datenblatt
AD73460
Analog Sigma-Delta Modulator
The AD73460 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73460, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to fS/2 = DMCLK/16
(Figure 3a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 3b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 3c).
(Sinc-cubed response) with nulls every multiple of DMCLK/256,
which is the decimation filter update rate. The final detail in
Figure 4d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented accord-
ing to the users requirements and available MIPS. The filtering
in Figures 4a through 4c is implemented in the AD73460.
fB = 4kHz
fSINIT = DMCLK/8
a. Analog Antialias Filter Transfer Function
SIGNAL TRANSFER FUNCTION
BAND
OF
INTEREST
a.
fS /2
DMCLK/16
NOISE TRANSFER FUNCTION
fB = 4kHz
fSINIT = DMCLK/8
b. Analog Sigma-Delta Modulator Transfer Function
NOISE-SHAPING
BAND
OF
INTEREST
b.
DIGITAL FILTER
fS /2
DMCLK/16
fB = 4kHz fSINTER = DMCLK/256
c. Digital Decimator Transfer Function
BAND
OF
INTEREST
c.
fS /2
DMCLK/16
Figure 3. Sigma-Delta Noise Reduction
Figure 4 shows the various stages of filtering that are employed
in a typical AD73460 application. In Figure 4a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial over-
sampling rate and the bandwidth of interest. In Figure 4b, the
signal and noise-shaping responses of the sigma-delta modulator
are shown. The signal response provides further rejection of any
high frequency signals while the noise-shaping will push the inher-
ent quantization noise to an out-of-band position. The detail of
Figure 4c shows the response of the digital decimation filter
fB = 4kHz fSFINAL = 8kHz fSINTER = DMCLK/256
d. Final Filter LPF (HPF) Transfer Function
Figure 4. DC Frequency Responses
Decimation Filter
The digital filter used in the AD73460 carries out two important
functions. Firstly, it removes the out-of-band quantization noise,
which is shaped by the analog modulator and secondly, it deci-
mates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits. Its Z
transform is given as: [(1Z32)/(1Z1)]3. This ensures a mini-
mal group delay of 25 µs.
–12–
REV. 0

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