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PDF AD73360 Data sheet ( Hoja de datos )
| Número de pieza | AD73360 | |
| Descripción | Six-Input Channel Analog Front End | |
| Fabricantes | Analog Devices | |
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a
Six-Input Channel
Analog Front End
AD73360
FEATURES
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
77 dB SNR
64 kS/s Maximum Sample Rate
–83 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel)
Programmable Input Gain
Flexible Serial Port which Allows Multiple Devices to
Be Connected in Cascade
Single (+2.7 V to +5.5 V) Supply Operation
80 mW Max Power Consumption at +2.7 V
On-Chip Reference
28-Lead SOIC and 44-Lead TQFP Packages
APPLICATIONS
General Purpose Analog Input
Industrial Power Metering
Motor Control
Simultaneous Sampling Applications
GENERAL DESCRIPTION
The AD73360 is a six-input channel analog front-end processor
for general purpose applications including industrial power
metering or multichannel analog inputs. It features six 16-bit
A/D conversion channels each of which provide 77 dB signal-to-
noise ratio over a dc to 4 kHz signal bandwidth. Each channel
also features a programmable input gain amplifier (PGA) with
gain settings in eight stages from 0 dB to 38 dB.
The AD73360 is particularly suitable for industrial power me-
tering as each channel samples synchronously, ensuring that there
is no (phase) delay between the conversions. The AD73360 also
features low group delay conversions on all channels.
An on-chip reference voltage is included and is programmable
to accommodate either 3 V or 5 V operation.
The sampling rate of the device is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73360 is available in 28-lead SOIC and 44-lead TQFP
packages.
FUNCTIONAL BLOCK DIAGRAM
VINP1
VINN1
VINP2
VINN2
SIGNAL
CONDITIONING
0/38dB
PGA
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
DECIMATOR
SDI
SDIFS
SCLK
VINP3
VINN3
REFCAP
REFOUT
VINP4
VINN4
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
REFERENCE
AD73360
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
SERIAL
I/O
PORT
RESET
MCLK
SE
VINP5
VINN5
SIGNAL
CONDITIONING
0/38dB
PGA
VINP6
VINN6
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
DECIMATOR
SDO
SDOFS
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD73360
Parameter
AD73360A
Min Typ Max
Unit
Test Conditions/Comments
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
VDD – 0.8
0
–0.5
10
VDD
0.8
VDD – 0.4
0
–0.3
VDD
0.4
V
V
µA
pF
V
V
µA
|IOUT| ≤ 100 µA
|IOUT| ≤ 100 µA
POWER SUPPLIES
AVDD1, AVDD2
DVDD
IDD8
4.5 5.5 V
4.5 5.5 V
See Table II
NOTES
1Operating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.
2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.
7Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table II. Current Summary (AVDD = DVDD = 5.5 V)
Conditions
Analog Digital
Current Current
Total
Current
(Typ)
ADCs Only On
REFCAP Only On
REFCAP and
REFOUT Only On
All Sections Off
All Sections Off
16
0.8
3.5
0.1
0
16
0
0
1.9
0.05
32
0.8
3.5
2.0
0.06
The above values are in mA and are typical values unless otherwise noted.
SE
1
0
0
0
0
MCLK
ON
YES
NO
NO
YES
NO
Comments
REFOUT Disabled
REFOUT Disabled
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
VREFCAP
VREFOUT
ADC
Maximum Input Range at VIN
Nominal Reference Level
Table III. Signal Ranges
3 V Power Supply
5VEN = 0
1.25 V ± 10%
1.25 V ± 10%
5 V Power Supply
5VEN = 0
1.25 V
1.25 V
5VEN = 1
2.5 V
2.5 V
1.64375 V p-p
1.1413 V p-p
1.64375 V p-p
1.1413 V p-p
3.2875 V p-p
2.2823 V p-p
REV. A
–5–
5 Page 
AD73360
FUNCTIONAL DESCRIPTION
General Description
The AD73360 is a six-channel, 16-bit, analog front end. It
comprises six independent encoder channels each featuring
signal conditioning, programmable gain amplifier, sigma-delta
A/D convertor and decimator sections. Each of these sections is
described in further detail below.
Encoder Channel
Each encoder channel consists of a signal conditioner, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input
antialias requirements are reduced such that a simple single pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Signal Conditioner
Each analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modula-
tor. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 in control
Registers D, E and F.
Table IV. PGA Settings for the Encoder Channel
IxGS2
0
0
0
0
1
1
1
1
IxGS1
0
0
1
1
0
0
1
1
IxGS0
0
1
0
1
0
1
0
1
Gain (dB)
0
6
12
18
20
26
32
38
ADC
Each channel has its own ADC consisting of an analog sigma-
delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and in-
creases the resolution.
Analog Sigma-Delta Modulator
The AD73360 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73360, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to fS/2 = DMCLK/16
(Figure 6a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 6b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 6c).
BAND
OF
INTEREST
a.
FS/2
DMCLK/16
NOISE-SHAPING
BAND
OF
INTEREST
b.
FS/2
DMCLK/16
DIGITAL FILTER
BAND
OF
INTEREST
c.
FS/2
DMCLK/16
Figure 6. Sigma-Delta Noise Reduction
REV. A
–11–
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