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AD73322 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD73322
Beschreibung Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD73322 Datasheet, Funktion
a Low Cost, Low Power CMOS
General-Purpose Dual Analog Front End
FEATURES
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows Up to Four Dual
Codecs to be Connected in Cascade Giving Eight
I/O Channels
Single (+2.7 V to +5.5 V) Supply Operation
73 mW Typ Power Consumption at 3.0 V
On-Chip Reference
28-Lead SOIC and 44-Lead LQFP Packages
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
Wireless Local Loop
GENERAL DESCRIPTION
The AD73322 is a dual front-end processor for general-purpose
applications including speech and telephony. It features two
16-bit A/D conversion channels and two 16-bit D/A conversion
channels. Each channel provides 77␣ dB signal-to-noise ratio
over a voiceband signal bandwidth. It also features an input-to-
output gain network in both the analog and digital domains.
This is featured on both codecs and can be used for impedance
matching or scaling when interfacing to Subscriber Line Inter-
face Circuits (SLICs).
The AD73322 is particularly suitable for a variety of applica-
tions in the speech and telephony area, including low bit rate,
high quality compression, speech enhancement, recognition, and
synthesis. The low group delay characteristic of the part makes
it suitable for single or multichannel active control applications.
VFBP1
VINP1
VINN1
VFBN1
VOUTP1
VOUTN1
REFOUT
REFCAP
VFBP2
VINP2
VINN2
VFBN2
VOUTP2
VOUTN2
AD73322
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2
DVDD
AD73322
ADC CHANNEL 1
SDI
SDIFS
DAC CHANNEL 1
REFERENCE
SPORT
SCLK
SE
RESET
ADC CHANNEL 2
MCLK
DAC CHANNEL 2
SDOFS
SDO
AGND1 AGND2 DGND
The A/D and D/A conversion channels feature programmable
input/output gains with ranges of 38 dB and 21 dB respectively.
An on-chip reference voltage is included to allow single-supply
operation. This reference is programmable to accommodate
either 3 V or 5 V operation.
The sampling rate of the codecs is programmable with four
separate settings, offering 64 kHz, 32 kHz, 16 kHz and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73322 is available in 28-lead SOIC and 44-lead LQFP
packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD73322 Datasheet, Funktion
AD73322
Parameter
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
AD73322A
Min Typ Max Units
+1 V
–1 V
16 Bits
25 µs
100 µs
DAC SPECIFICATIONS
Maximum Voltage Output Swing2
Single-Ended
Differential
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
Differential
Output Bias Voltage
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion) at 0 dBm0
PGA = 6 dB
Total Harmonic Distortion at 0 dBm0
PGA = 6 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk DAC-to-ADC
3.156
3.17
6.312
9.19
2.1908
0
4.3918
6.02
2.4
+0.4
± 0.1
77
–80
–85
–85
–90
V p-p
dBm
V p-p
dBm
V p-p
dBm
V p-p
dBm
V
dB
dB
dB
dB
dB
dBm0
dB
DAC-to-DAC
Power Supply Rejection
Group Delay4, 5
Output DC Offset2, 7
Minimum Load Resistance, RL2, 8
Single-Ended
Differential
Maximum Load Capacitance, CL2, 8
Single-Ended
Differential
FREQUENCY RESPONSE
(ADC and DAC)9 Typical Output
Frequency (Normalized to FS)
0
0.03125
0.0625
0.125
0.1875
0.25
0.3125
0.375
0.4375
> 0.5
–77
–100
dB
dB
–65 dB
25 µs
50 µs
+12 mV
150
150
500 pF
100 pF
0
–0.1
–0.25
–0.6
–1.4
–2.8
–4.5
–7.0
–9.5
< –12.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Test Conditions/Comments
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
5VEN = 1
PGA = 6 dB
Max Output = (3.156/2.4) × VREFCAP
PGA = 6 dB
Max Output = 2 × ([3.156/2.4] × VREFCAP)
PGA = 6 dB
PGA = 6 dB
REFOUT Unloaded
1.0 kHz, 0 dBm0; Unloaded
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to Figure 8
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0;
Input Amplifiers Bypassed
Input Amplifiers Included In Input Channel
DAC1 Output Signal Level: AGND; DAC2
Output Signal Level: 1.0 kHz, 0 dBm0
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Interpolator Bypassed
–6– REV. B

6 Page









AD73322 pdf, datenblatt
AD73322
TERMINOLOGY
Absolute Gain
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at
0 dBm0 for the ADC. The absolute gain specification is used for
gain tracking error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.
Gain Tracking Error
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group Delay
Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 300 Hz–3400 Hz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n is equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
The sample rate can be chosen from a list of four that are fixed
relative to the DMCLK. Sample rate is set by programming bits
DIR0-1 in Control Register B of each channel.
SNR+THD
Signal-to-noise ratio plus total harmonic distortion is defined to
be the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.
ABBREVIATIONS
ADC
Analog-to-Digital Converter.
AFE Analog Front End.
AGT
Analog Gain Tap.
ALB Analog Loop-Back.
BW Bandwidth.
CRx A Control Register where x is a placeholder for an
alphabetic character (A–E). There are five read/
write control registers on the AD73322—desig-
nated CRA through CRE.
CRx:n
A bit position, where n is a placeholder for a nu-
meric character (0–7), within a control register,
where x is a placeholder for an alphabetic charac-
ter (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.
DAC
Digital-to-Analog Converter.
DGT
Digital Gain Tap.
DLB
Digital Loop-Back.
DMCLK
Device (Internal) Master Clock. This is the inter-
nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip mas-
ter clock divider.
FS Full Scale.
FSLB
Frame Sync Loop-Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and out-
put occur simultaneously. In the case of Non-
FSLB, SDOFS and SDO are connected to the
Rx Port of the DSP while SDIFS and SDI are
connected to the Tx Port.
PGA
Programmable Gain Amplifier.
SC Switched Capacitor.
SLB Sport Loop-Back
SNR
Signal-to-Noise Ratio.
SPORT Serial Port.
THD
Total Harmonic Distortion.
VBW
Voice Bandwidth.
–12–
REV. B

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