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PDF AD73311 Data sheet ( Hoja de datos )
| Número de pieza | AD73311 | |
| Descripción | Low Cost/ Low Power CMOS General Purpose Analog Front End | |
| Fabricantes | Analog Devices | |
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a
Low Cost, Low Power CMOS
General Purpose Analog Front End
AD73311
FEATURES
16-Bit A/D Converter
16-Bit D/A Converter
Programmable Input/Output Sample Rates
75 dB ADC SNR
70 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows up to 8 Devices
to Be Connected in Cascade
Single (+2.7 V to +5.5 V) Supply Operation
50 mW Max Power Consumption at 2.7 V
On-Chip Reference
20-Lead SOIC/SSOP Package
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound & Vibration
Data Communications
GENERAL DESCRIPTION
The AD73311 is a complete front-end processor for general
purpose applications including speech and telephony. It features
a 16-bit A/D conversion channel and a 16-bit D/A conversion
channel. Each channel provides 70 dB signal-to-noise ratio over
a voiceband signal bandwidth. The final channel bandwidth can
be reduced, and signal-to-noise ratio improved, by external
digital filtering in a DSP engine.
The AD73311 is suitable for a variety of applications in the
speech and telephony area including low bit rate, high quality
compression, speech enhancement, recognition and synthesis.
The low group delay characteristic of the part makes it suitable
for single or multichannel active control applications.
The gains of the A/D and D/A conversion channels are pro-
grammable over 38 dB and 21 dB ranges respectively. An
on-chip reference voltage is included to allow single supply
operation. A serial port (SPORT) allows easy interfacing of
single or cascaded devices to industry standard DSP engines.
The AD73311 is available in both 20-lead SOIC and SSOP
packages.
AVDD1
FUNCTIONAL BLOCK DIAGRAM
AVDD2
DVDD
VINP
VINN
VOUTP
VOUTN
REFCAP
REFOUT
0/38dB
PGA
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS FILTER
REFERENCE
ANALOG
SIGMA-DELTA
MODULATOR
SWITCHED-
CAPACITOR
LOW-PASS FILTER
1-BIT
DAC
DIGITAL
SIGMA-DELTA
MODULATOR
DECIMATOR
INTERPOLATOR
SERIAL
I/O
PORT
AD73311
AGND1
AGND2
DGND
SDI
SDIFS
SCLK
SDO
SDOFS
SE
MCLK
RESET
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD73311
Parameter
AD73311A
Min Typ Max
Unit Test Conditions/Comments
DAC SPECIFICATIONS (Continued)
Power Supply Rejection
Group Delay4, 5
Output DC Offset2, 7
Minimum Load Resistance, RL2, 8
Single-Ended
Differential
Maximum Load Capacitance, CL2, 8
Single-Ended
Differential
–55 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
25 µs 64 kHz Input Sample Rate, Interpolator
Bypassed (CRE:5 = 1)
+30 mV PGA = 6 dB
150 Ω
150 Ω
500 pF
100 pF
FREQUENCY RESPONSE
(ADC AND DAC)9 Typical Output
0 Hz
2000 Hz
4000 Hz
8000 Hz
12000 Hz
16000 Hz
20000 Hz
24000 Hz
28000 Hz
> 32000 Hz
0
–0.1
–0.25
–0.6
–1.4
–2.8
–4.5
–7.0
–9.5
< –12.5
dB
dB
dB
dB
dB
dB
dB Channel Frequency Response Is
dB Programmable by Means of External
dB Digital Filtering
dB
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance
LOGIC OUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
VDD – 0.8
0
–0.5
10
VDD – 0.4
0
–0.3
VDD
0.8
VDD
0.4
V
V
µA
pF
V |IOUT| < 100 µA
V |IOUT| < 100 µA
µA
POWER SUPPLIES
AVDD1, AVDD2
DVDD
IDD10
4.5 5.5 V
4.5 5.5 V
See Table II
NOTES
1Operating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.
2Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise stated).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.
7Between VOUTP and VOUTN.
8At VOUT output.
9Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
10Test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
REV. B
–5–
5 Page 
AD73311
TERMINOLOGY
Absolute Gain
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at
0 dBm0 for the ADC. The absolute gain specification is used for
gain tracking error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel
to an adjacent channel. It is defined as the ratio of the amplitude
of the coupled signal to the amplitude of the input signal.
Crosstalk is expressed in dB.
Gain Tracking Error
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group Delay
Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 300 Hz–3400 Hz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
It is fixed relative to the DMCLK (= DMCLK/256) and there-
fore may only be changed by changing the DMCLK.
SNR+THD
Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.
ABBREVIATIONS
ADC
Analog-to-Digital Converter.
ALB Analog Loop-Back.
BW Bandwidth.
CRx A Control Register where x is a placeholder for an
alphabetic character (A–E). There are five read/
write control registers on the AD73311—desig-
nated CRA through CRE.
CRx:n
A bit position, where n is a placeholder for a nu-
meric character (0–7), within a control register;
where x is a placeholder for an alphabetic charac-
ter (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.
DAC
Digital-to-Analog Converter.
DLB
Digital Loop-Back.
DMCLK
Device (Internal) Master Clock. This is the inter-
nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip mas-
ter clock divider.
FSLB
Frame Sync Loop Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and out-
put occur simultaneously. In the case of Non-
FSLB, SDOFS and SDO are connected to the
Rx Port of the DSP while SDIFS and SDI are
connected to the Tx Port.
PGA
Programmable Gain Amplifier.
SC Switched Capacitor.
SNR
Signal-to-Noise Ratio.
SPORT Serial Port.
THD
Total Harmonic Distortion.
VBW
Voice Bandwidth.
REV. B
–11–
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