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AD7304 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7304
Beschreibung +3 V/+5 V/ Rail-to-Rail Quad/ 8-Bit DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD7304 Datasheet, Funktion
FEATURES
Four 8-bit DACs in one package
+3 V, +5 V, and ±5 V operation
Rail-to-rail REF input to voltage output swing
2.6 MHz reference multiplying bandwidth
Internal power-on reset
SPI serial interface-compatible—AD7304
Fast parallel interface—AD7305
40 µA power shutdown
APPLICATIONS
Automotive output span voltage
Instrumentation, digitally controlled calibration
Pin-compatible AD7226 replacement when VDD < 5.5 V
GENERAL DESCRIPTION
The AD7304/AD73051 are quad, 8-bit DACs that operate from
a single +3 V to +5 V supply, or ±5 V supplies. The AD7304 has
a serial interface, while the AD7305 has a parallel interface.
Internal precision buffers swing rail-to-rail. The reference input
range includes both supply rails, allowing for positive or negative
full-scale output voltages. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V, consuming less than
9 mW from a 3 V supply.
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail VREF input to
DAC VOUT allows for a full-scale voltage set equal to the positive
supply, VDD, the negative supply, VSS, or any value in between.
The AD7304’s doubled-buffered serial data interface offers high
speed, 3-wire, SPI®-, and microcontroller-compatible inputs
using data in (SDI), clock (CLK), and chip select (CS) pins.
Additionally, an internal power-on reset sets the output to zero
scale.
The parallel input AD7305 uses a standard address decode
along with the WR control line to load data into the input
registers.
The double-buffered architecture allows all four input registers
to be preloaded with new values, followed by an LDAC control
strobe that copies all the new data into the DAC registers,
thereby updating the analog output values.
_____________________________________________________
1 Protected under Patent No. 5684481.
3 V/5 V, Rail-to-Rail
Quad, 8-Bit DAC
AD7304/AD7305
FUNCTIONAL BLOCK DIAGRAMS
VDD
VREFB VREFA
CS
SDI/SHDN
CLK
PWR-ON
RESET
8
INPUT 8 DAC A 8
REG A
REG
INPUT 8 DAC B 8
REG B
REG
SERIAL
REG
INPUT 8 DAC C 8
REG C
REG
INPUT 8 DAC D 8
REG D
REG
DAC A
DAC B
DAC C
DAC D
AD7304
VOUTA
VOUTB
VOUTC
VOUTD
VSS GND
CLR LDAC VREFC VREFD
Figure 1.
VDD
VREF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
WR
A0/SHDN
A1
PWR-ON
RESET
8
INPUT 8 DAC A 8
REG A
REG
INPUT 8 DAC B 8
REG B
REG
8
DECODE
INPUT 8 DAC C 8
REG C
REG
INPUT 8 DAC D 8
REG D
REG
DAC A
DAC B
DAC C
DAC D
AD7305
LDAC
Figure 2.
VSS
GND
VOUTA
VOUTB
VOUTC
VOUTD
When operating from less than 5.5 V, the AD7305 is
pin-compatible with the popular industry-standard AD7226.
An internal power-on reset places both parts in the zero-scale
state at turn-on. A 40 µA power shutdown (SHDN) feature is
activated on both parts by three-stating the SDI/SHDN pin on
the AD7304 and three-stating the A0/SHDN address pin on the
AD7305.
The AD7304/AD7305 are specified over the extended industrial
−40°C to +85°C and the automotive −40°C to +125°C
temperature ranges. AD7304s are available in a wide-body
16-lead SOIC (R-16) package. The parallel input AD7305 is
available in the wide-body 20-lead SOIC (R-20) surface-mount
package. For ultracompact applications, the thin 1.1 mm,
16-lead TSSOP (RU-16) package is available for the AD7304,
while the 20-lead TSSOP (RU-20) houses the AD7305.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD7304 Datasheet, Funktion
AD7304/AD7305
SDI SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CLK
CS
tCSS
LDAC
tLD1
tCSH
tLD2
SDI
CLK
LDAC
CLR
FS
VOUT
ZS
tDS
tCL
tDH
tCH
tLDW
tS
Figure 4. AD7304 General Timing Diagram
tCLRW
±1 LSB
ERROR BAND
tS
SDI/SHDN
IDD
tSDN
tSDR
Figure 5. AD7304 Timing Diagram Zoom In
Table 4. AD7304 Control Logic Truth Table
CS 1 CLK1 LDAC CLR1 Serial Shift Register Function
HX
L +
+ L
H
H
H
H No effect
H Data advanced 1 bit
H No effect
HX
HX
HX
L
H
H
H No effect
– No effect
+ No effect
Input REG Function
No effect
No effect
Updated with SR contents2
Latched with SR contents2
Loaded with 0x00
Latched with 0x00
DAC Register Function
No effect
No effect
No effect
All input register contents transferred3
Loaded with 0x00
Latched with 0x00
1 + positive logic transition; – negative logic transition; X Don’t Care.
2 One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1).
3 LDAC is a level-sensitive input.
Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format
MSB LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7304 SAC SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become
high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed
in shutdown mode.
Rev. C | Page 6 of 20

6 Page









AD7304 pdf, datenblatt
AD7304/AD7305
1
VDD = +5V
VSS = –5V
0.1
0.01
0.001
20
3.0
2.4
1.8
100 1k 10k
FREQUENCY (Hz)
Figure 22. THD vs. Frequency
100k
VDD = +5V
VSS = –5V
VREF = +4V
DATA = 0xFF
1.2
0.6
0
1 10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 23. Output Noise Voltage Density vs. Frequency
VOUTB
CLK
VDD = +5V
VSS = –5V
VREF = +2.5V
DAC A = 0xFF
DAC B = 0x00
F = 2MHz
50ns/DIV
50ns/DIV
Figure 24. Digital Feedthrough
VOUT
CS
VDD = +5V
VSS = –5V
VREF = +2.5V
F = 1MHz
DATA = 0x80
0x7F
Figure 25. Midscale Transition Glitch
40
20
VDD = +5V
VSS = –5V
0
VREF = 50mV rms
DAC A DATA = 0xFF
–20 DAC B, DAC C, DAC D DATA = 0x00
–40
–60
–80
–100
–120
–140
VOUTB
CT = 20 LOG VREF
–160
100
1k 10k 100k 1M
FREQUENCY (Hz)
10M
Figure 26. Crosstalk vs. Frequency
60
–PSRR, VSS = –5V ± ∆10%
50 +PSRR, VDD = +5V ± ∆10%
40
–PSRR, VSS = –3V ± ∆10%
30 +PSRR, VDD = +3V ± ∆10%
20
10
0
10
DATA = 0x80
TA = +25°C
100 1k 10k
FREQUENCY (Hz)
100k
Figure 27. Power-Supply Rejection vs. Frequency
Rev. C | Page 12 of 20

12 Page





SeitenGesamt 20 Seiten
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