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PDF AD7302 Data sheet ( Hoja de datos )
| Número de pieza | AD7302 | |
| Descripción | 2.7 V to 5.5 V/ Parallel Input Dual Voltage Output 8-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Two 8-Bit DACs In One Package
20-Lead DIP/SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer
Rail-to-Rail Operation
Low Power Operation 3 mA max @ 3.3 V
Power-Down to 1 A max @ 25؇C
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
2.7 V to 5.5 V, Parallel Input
Dual Voltage Output 8-Bit DAC
AD7302
FUNCTIONAL BLOCK DIAGRAM
AD7302
INPUT
REGISTER
DAC
REGISTER
I DAC A
I/V
VOUTA
D7
D0
INPUT
REGISTER
DAC
REGISTER
I DAC B
I/V
VOUTB
A/B
WR
CONTROL
LOGIC
CS
MUX
POWER ON
RESET
÷2 AGND
PD CLR
LDAC
REFIN VDD DGND
GENERAL DESCRIPTION
The AD7302 is a dual, 8-bit voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision
output buffers allow the DAC outputs to swing rail to rail. The
AD7302 has a parallel microprocessor and DSP-compatible
interface with high speed registers and double buffered interface
logic. Data is loaded to the registers on the rising edge of CS or
WR and the A/B pin selects either DAC A or DAC B.
Reference selection for AD7302 can be either an internal
reference derived from the VDD or an external reference applied
at the REFIN pin. Both DACs can be simultaneously updated
using the asynchronous LDAC input and can be cleared by
using the asynchronous CLR input.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump-
tion is less than 10 mW at 3.3 V, reducing to 3 µW in power-
down mode.
The AD7302 is available in a 20-pin plastic dual-in-line package,
20-lead SOIC and a 20-lead TSSOP package.
PRODUCT HIGHLIGHTS
1.␣ Low Power, Single Supply Operation. This part operates
from a single +2.7 V to +5.5 V supply and typically consumes
15 mW at 5 V, making it ideal for battery powered applications.
2.␣ The on-chip output buffer amplifiers allow the outputs of the
DACs to swing rail to rail with a settling time of typically 1.2 µs.
3.␣ Internal or external reference capability.
4.␣ High speed parallel interface.
5. Power-Down Capability. When powered down the DAC
consumes less than 1 µA at 25°C.
6. Packaged in 20-lead DIP, SOIC and TSSOP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
1 page  
AD7302
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1-8 D7–D0
9 CS
10 WR
11 A/B
12 PD
13 LDAC
14 CLR
15 VDD
16 REFIN
17 AGND
18 VOUTB
19 VOUTA
20 DGND
Parallel Data Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of CS
and WR.
Chip Select. Active low logic input.
Write Input. WR is an active low logic input used in conjunction with CS and A/B to write data to the selected
DAC register.
DAC Select. Address pin used to select writing to either DAC A or DAC B.
Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with
the contents of their DAC registers. If LDAC is permanently tied low, the DACs are updated on the rising
edge of WR.
Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all
zeroes and the DAC outputs are cleared to zero volts.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND.
External Reference Input. This can used as the reference for both DACs. The range on this reference input is
1 V to VDD/2. If REFIN is directly tied to VDD the internal VDD/2 reference is selected.
Analog Ground reference point and return point for all analog current on the part.
Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output.
Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output.
Digital Ground reference point and return point for all digital current on the part.
PIN CONFIGURATION
(MSB) DB7 1
20 DGND
DB6 2
DB5 3
19 VOUTA
18 VOUTB
DB4 4
17 AGND
DB3 5 AD7302 16 REFIN
DB2
6
TOP VIEW
(Not to Scale)
15
VDD
DB1 7
14 CLR
(LSB) DB0 8
13 LDAC
CS 9
12 PD
WR 10
11 A/B
REV. 0
–5–
5 Page 
␣ ␣ VREF is the voltage applied to the external REFIN pin when
the external reference is selected and is VDD/2 if the
internal reference is used.
Table I. Output Voltage for Selected Input Codes
Digital Input
MSB . . . LSB
Analog Output
1111 1111
1111 1110
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
2 × 255/256 × VREF V
2 × 254/256 × VREF V
2 × 129/256 × VREF V
VREF V
2 × 127/256 × VREF V
2 × VREF/256␣ V
0V
2.VREF
VREF
0
VDD = 3 TO 5V
0.1µF 10µF
AD7302
REF IN
VDD AGND DGND
VOUTA
AD7302
CLR
PD
VOUTB
D7–D0
A/B CS WR LDAC
VDD
DATA BUS CONTROL INPUTS
VOUTA
VOUTB
Figure 27. Typical Configuration Selecting the Internal
Reference
Figure 28 shows a typical setup for the AD7302 when using an
external reference. The reference range for the AD7302 is from
1 V to VDD/2 V. Higher values of reference can be incorporated,
but will saturate the output at both the top and bottom end of
the transfer function. There is a gain of two from input to output
on the AD7302. Suitable references for 5 V operation are the
AD780 and REF192. For 3 V operation a suitable external
reference would be the AD589 a 1.23 V bandgap reference.
VDD = 3 TO 5V
0.1µF 10µF
DAC INPUT
CODE
00
01
7F 80 81
FE FF
Figure 26. DAC Transfer Function
Figure 27 shows a typical setup for the AD7302 when using its
internal reference. The internal reference is selected by tying the
REFIN pin to VDD. Internally in the reference section there is a
reference detect circuit that will select the internal VDD/2 based
on the voltage connected to the REFIN pin. If REFIN is within
a threshold voltage of a PMOS device (approximately 1 V) of
VDD the internal reference is selected. When the REFIN voltage
is more than 1 V below VDD, the externally applied voltage at
this pin is used as the reference for the DAC. The internal
reference on the AD7302 is VDD/2, the output current to voltage
converter within the AD7302 provides a gain of two. Thus the
output range of the DAC is from 0 V to VDD, based on Table I.
VIN
EXT REF VOUT
GND
0.1µF
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
VDD
REF IN
CLR
PD
D7–D0
VDD AGND DGND
VOUTA
AD7302
VOUTB
A/B CS WR LDAC
DATA BUS CONTROL INPUTS
VOUTA
VOUTB
Figure 28. Typical Configuration Using An External
Reference
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7302.PDF ] | |
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