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AD7273 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7273
Beschreibung 10-/12-Bit ADCs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD7273 Datasheet, Funktion
FEATURES
Throughput rate: 3 MSPS
Specified for VDD of 2.35 V to 3.6 V
Power consumption
11.4 mW at 3 MSPS with 3 V supplies
Wide input bandwidth
70 dB SNR at 1 MHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Temperature range: −40°C to +125°C
Power-down mode: 0.1 μA typ
8-lead TSOT package
8-lead MSOP package
GENERAL DESCRIPTION
The AD7273/AD7274 are 10-/12-bit, high speed, low power,
successive approximation ADCs, respectively. The parts operate
from a single 2.35 V to 3.6 V power supply and feature
throughput rates of up to 3 MSPS. Each part contains a low
noise, wide bandwidth track-and-hold amplifier that can handle
input frequencies in excess of 55 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS, and the conversion is also initiated at this
point. The conversion rate is determined by the SCLK. There
are no pipeline delays associated with these parts.
The AD7273/AD7274 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
The reference for the parts is applied externally and can be in
the range of 1.4 V to VDD. This allows the widest dynamic input
range to the ADC.
3 MSPS,10-/12-Bit
ADCs in 8-Lead TSOT
AD7273/AD7274
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
VIN
VREF
10-/12-BIT
SUCCESSIVE
T/H APPROXIMATION
ADC
CONTROL
LOGIC
AD7273/AD7274
DGND
Figure 1.
SCLK
SDATA
CS
Table 1.
Part Number
AD72731
AD72741
AD7276
AD7277
AD7278
Resolution
10
12
12
10
8
Package
8-lead MSOP 8-Lead TSOT
8-lead MSOP 8-Lead TSOT
8-lead MSOP 6-Lead TSOT
8-lead MSOP 6-Lead TSOT
8-lead MSOP 6-Lead TSOT
1 Parts contain external reference pin.
PRODUCT HIGHLIGHTS
1. 3 MSPS ADCs in an 8-lead TSOT package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management.
Allows maximum power efficiency at low throughput rates.
4. Reference can be driven up to the power supply.
5. No pipeline delay.
6. The parts feature a standard successive approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.






AD7273 Datasheet, Funktion
AD7273/AD7274
Parameter
POWER RQUIREMENTS
VDD
IDD
Normal Mode (Static)
Normal Mode (Operational)
Partial Power-Down Mode (Static)
Full Power-Down Mode (Static)
Power Dissipation5
Normal Mode (Operational)
Partial Power-Down
Full Power-Down
B Grade1
2.35/3.6
0.6
5
3.2
34
2
10
18
9.6
102
7.2
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
Unit 2
Test Conditions/Comments
V min/V max
mA typ
mA max
mA typ
μA typ
μA max
μA max
Digital I/Ps = 0 V or VDD
VDD = 3 V, SCLK on or off
VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
−40°C to +85°C, typically 0.1 μA
85°C to 125°C
mW max
mW typ
μW max
μW max
VDD = 3.6 V , fSAMPLE = 3 MSPS
VDD = 3 V
VDD = 3 V
VDD = 3.6 V, −40°C to +85°C
Rev. 0 | Page 6 of 28

6 Page









AD7273 pdf, datenblatt
AD7273/AD7274
–70
–80
–90
–100
100mV p-p SINE WAVE ON AVDD
NO DECOUPLING
–110
0
500
1000
1500
2000
2500
SUPPLY RIPPLE FREQUENCY (MHz)
3000
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple
Frequency Without Decoupling
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
VDD = 3V
500 1000 1500 2000 2500 3000 3500 4000
CODES
Figure 17. AD7274 INL Performance
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
VDD = 3V
500 1000 1500 2000 2500 3000 3500 4000
CODES
Figure 18. AD7274 DNL Performance
1.0
0.8
0.6
0.4 POSITIVE INL
0.2
0
–0.2
–0.4
NEGATIVE INL
–0.6
–0.8
–1.0
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
REFERENCE VOLTAGE (V)
Figure 19. Change in INL vs. Reference Voltage, 3 V Supply
1.0
0.8
0.6
POSITIVE DNL
0.4
0.2
0
–0.2
–0.4
–0.6
NEGATIVE DNL
–0.8
–1.0
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
REFERENCE VOLTAGE (V)
Figure 20. Change in DNL vs. Reference Voltage, 3 V Supply
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0
VDD = 3V
VDD = 3.6V
VDD = 2.5V
10 20 30 40
SCLK FREQUENCY (MHz)
Figure 21. Maximum Current vs. Supply Voltage
for Different SCLK Frequencies
50
Rev. 0 | Page 12 of 28

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