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AD7266 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7266
Beschreibung Differential Input/ Dual 2 MSPS/ 12-Bit/ 3-Channel SAR ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 17 Seiten
AD7266 Datasheet, Funktion
Preliminary Technical Data
FEATURES
Dual 12-bit, 3-channel ADC
Fast throughput rate: 2 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power: 12 mW max at 1.5 MSPS with 3 V supplies
30 mW max at 2 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
On-chip reference: 2.5 V
–40°C to +125°C operation
Flexible power/throughput rate management
Simultaneous conversion/read
No pipeline delays
High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 1 µA max
32-lead LFCSP and TQFP packages
GENERAL DESCRIPTION
The AD72661 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 2 MSPS. The
device contains two ADCs, each preceded by a 3-channel multi-
plexer, and a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 10 MHz.
The conversion process and data acquisition are controlled using
standard control inputs, allowing easy interfacing to microproces-
sors or DSPs. The input signal is sampled on the falling edge of CS;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined delays
associated with the part.
The AD7266 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 5 V supplies and a
2 MSPS throughput rate, the part consumes 4 mA maximum. The
part also offers flexible power/throughput rate management when
operating in sleep mode.
The analog input range for the part can be selected to be a 0 V to
VREF range or a 2VREF range with either straight binary or twos
complement output coding. The AD7266 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre-
ferred. This external reference range is 100 mV to 2.5 V. The
AD7266 is available in 32-lead lead frame chip scale (LFCSP) and
thin quad flat (TQFP) packages.
1Protected by U.S. Patent No. 6,681,332.
Rev. PrG
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Differential Input, Dual 2 MSPS,
12-Bit, 3-Channel SAR ADC
AD7266
FUNCTIONAL BLOCK DIAGRAM
REF SELECT
DCAPA
AVDD
DVDD
REF
BUF
AD7266
VA1
VA2
VA3
VA4
MUX
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
DOUTA
VA5
VA6
SCLK
CS
RANGE
CONTROL
LOGIC
SGL/DIFF
A0
A1
VB1 A2
VB2
VDRIVE
VB3
VB4
MUX
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
OUTPUT
DRIVERS
DOUTB
VB5 ADC
VB6
BUF
AGND AGND AGND DCAPB
DGND DGND
Figure 1
PRODUCT HIGHLIGHTS
1. The AD7266 features two complete ADC functions that allow
simultaneous sampling and conversion of two channels. Each
ADC has 2 analog inputs, 3 fully differential pairs, or 6 single-
ended channels as programmed. The conversion result of both
channels is available simultaneously on separate data lines, or
in succession on one data line if only one serial port is
available.
2. High Throughput with Low Power Consumption
The AD7266 offers a 1.5 MSPS throughput rate with 8 mW
maximum power consumption when operating at 3 V.
3. Flexible Power/Throughput Rate Management
The conversion rate is determined by the serial clock, allowing
power consumption to be reduced as conversion time is re-
duced through an SCLK frequency increase. Power efficiency
can be maximized at lower throughput rates if the part enters
sleep between conversions.
4. No Pipeline Delay
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a CS
input and once off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD7266 Datasheet, Funktion
AD7266
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Preliminary Technical Data
DGND 1
REF SELECT 2
AVDD 3
DCAPA 4
AGND 5
AGND 6
VA1 7
VA2 8
32 31 30 29 28 27 26 25
AD7266
TOP VIEW
(Not to Scale)
24 A1
23 A2
22 SGL/DIFF
21 RANGE
20 DCAPB
19 AGND
18 VB1
17 VB2
9 10 11 12 13 14 15 16
Figure 2. AD7266 Pin Configuration
Table 4. AD7266 Pin Function Descriptions
Pin No. Mnemonic Description
4, 20
DCAPA,
DCAPB
Decoupling capacitors (470nF recommended) are connected to these pins to decouple the reference buffer for
each respective ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a
system. The range of the external reference is dependent on the analog input range selected. See the Reference
Configuration Options section.
7–12
VA1–VA6
Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
18–13 VB1–VB6
Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
27 SCLK
Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock
is also used as the clock source for the conversion process.
5, 6, 19 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not
be more than 0.3 V apart, even on a transient basis.
32 DVDD
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7266. The DVDD
and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a
transient basis. This supply should be decoupled to DGND.
31 VDRIVE
Logic power supply input. The voltage supplied at this pin determines at what voltage the interface will operate.
This pin should be decoupled to DGND. The voltage at this pin may be different to that at AVDD and DVDD but
should never exceed either by more than 0.3 V.
1, 29 DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
3 AVDD Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The
AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis. This supply should be decoupled to AGND.
26 CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266
and frames the serial data transfer.
30, 28
DOUTA,
DOUTB
Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are clocked out on the
falling edge of the SCLK input and 14 SCLKs are required to access the data. The data appears on both pins
simultaneously from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros
followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles
rather than 14, then two trailing zeros will appear after the 12 bits of data. If CS is held low for a further 16 SCLK
cycles after this on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data
from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB alone
using only one serial port. See the Serial Interface section.
Rev. PrG | Page 6 of 17

6 Page









AD7266 pdf, datenblatt
AD7266
TRANSFER FUNCTIONS
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096.
The ideal transfer characteristic for the AD7266 when straight
binary coding is output is shown in Figure 6, and the ideal
transfer characteristic for the AD7266 when twos complement
coding is output is shown in Figure 7.
111...111
111...110
111...000
011...111
1LSB = VREF/4096
000...010
000...001
000...000
0V 1LSB
VREF – 1LSB
ANALOG INPUT
Figure 6. Straight Binary Transfer Characteristic
011...111
011...110
1LSB = 2 × VREF/4096
000...001
000...000
111...111
100...010
100...001
100...000
–VREF + 1LSB VREF – 1LSB
+VREF – 1 LSB
ANALOG INPUT
Figure 7. Twos Complement Transfer Characteristic with VREF ±VREF Input
Range
Preliminary Technical Data
DIGITAL INPUTS
The digital inputs applied to the AD7266 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
VDD + 0.3 V limit as on the analog inputs. See the Absolute
Maximum Ratings. Another advantage of SCLK, RANGE,
A0–A2, and CS not being restricted by the VDD + 0.3 V limit is
that power supply sequencing issues are avoided. If one of these
digital inputs is applied before VDD, there is no risk of latch-up,
as there would be on the analog inputs if a signal greater than
0.3 V were applied prior to VDD.
VDRIVE
The AD7266 also has the VDRIVE feature, which controls the
voltage at which the serial interface operates. VDRIVE allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7266 was operated with a VDD of 5 V, the
VDRIVE pin could be powered from a 3 V supply, allowing a large
dynamic range with low voltage digital processors. For example,
the AD7266 could be used with the 2 × VREF input range, with a
VDD of 5 V while still being able to interface to 3 V digital parts.
Rev. PrG | Page 12 of 17

12 Page





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