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PDF AD7233 Data sheet ( Hoja de datos )
| Número de pieza | AD7233 | |
| Descripción | LC2MOS 12-Bit Serial Mini-DIP DACPORT | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
12-Bit CMOS DAC with
On-Chip Voltage Reference
Output Amplifier
–5 V to +5 V Output Range
Serial Interface
300 kHz DAC Update Rate
Small Size: 8-Pin Mini-DIP
Nonlinearity: ؎1/2 LSB TMIN to TMAX
Low Power Dissipation: 100 mW typ
APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
LC2MOS
12-Bit Serial Mini-DIP DACPORT
AD7233
FUNCTIONAL BLOCK DIAGRAM
VDD
2R 2R
AD7233
12-BIT
DAC
12
DAC
LATCH
12
INPUT SHIFT
REGISTER
VOUT
GND
VSS
GENERAL DESCRIPTION
The AD7233 is a complete 12-bit, voltage-output, digital-to-
analog converter with output amplifier and Zener voltage refer-
ence all in an 8-lead package. No external trims are required to
achieve full specified performance. The data format is two’s
complement, and the output range is –5 V to +5 V.
The AD7233 features a fast, versatile serial interface which al-
lows easy connection to both microcomputers and 16-bit digital
signal processors with serial ports. When the SYNC input is
taken low, data on the SDIN pin is clocked into the input shift
register on each falling edge of SCLK. On completion of the
16-bit data transfer, bringing LDAC low updates the DAC latch
with the lower 12 bits of data and updates the output. Alterna-
tively, LDAC can be tied permanently low, and in this case the
DAC register is automatically updated with the contents of the
shift register when all sixteen data bits have been clocked in.
The serial data may be applied at rates up to 5 MHz allowing a
DAC update rate of 300 kHz.
For applications which require greater flexibility and unipolar
output ranges with single supply operation, please refer to the
AD7243 data sheet.
The AD7233 is fabricated on Linear Compatible CMOS
(LC2MOS), an advanced, mixed-technology process. It is pack-
aged in an 8-lead DIP package.
SDIN SCLK SYNC LDAC
PRODUCT HIGHLIGHTS
1. Complete 12-Bit DACPORT®.
2. The AD7233 is a complete, voltage output, 12-bit DAC on a
single chip. This single-chip design is inherently more reli-
able than multichip designs.
3. Simple 3-wire interface to most microcontrollers and DSP
processors.
4. DAC Update Rate—300 kHz.
5. Space Saving 8-Lead Package.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
There are two ways in which the DAC latch and hence the ana-
log output may be updated. The status of the LDAC input is
examined after SYNC is taken low. Depending on its status, one
of two update modes is selected.
If LDAC = 0 then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto-
matically when the last bit in the serial data stream is clocked in.
The update thus takes place on the sixteenth falling SCLK edge.
AD7233
If LDAC = 1 then the automatic update is disabled and the
DAC latch is updated by taking LDAC low any time after the
16-bit data transfer is complete. The update now occurs on the
falling edge of LDAC. This facility is useful for simultaneous
update in multi-DAC systems. Note that the LDAC input must
be taken back high again before the next data transfer is initiated.
SYNC
SCLK
SDIN
LDAC
SCLK
SYNC
SDIN
LDAC
RESET
–16
COUNTER/
DECODER
GATING
SIGNAL
GATED
SCLK
INPUT SHIFT REGISTER (16 BITS)
AUTO-UPDATE
CIRCUITRY
DAC LATCH (12 BITS)
Figure 2. Simplified Loading Structure
t1
t2
t4
DB15
DB14
DB13
DB12
DON'T CARE DON'T CARE DON'T CARE DON'T CARE
DB11
MSB
t5
t3
DB1
DB0
LSB
t6 t7
t8
Figure 3. Timing Diagram
REV. A
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD7233.PDF ] | |
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